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@@ -0,0 +1,86 @@
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+/*
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+ *
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+ * arch/arm/mach-u300/timer.c
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+ *
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+ *
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+ * Copyright (C) 2007-2009 ST-Ericsson AB
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+ * License terms: GNU General Public License (GPL) version 2
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+ * Timer COH 901 328, runs the OS timer interrupt.
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+ * Author: Linus Walleij <linus.walleij@stericsson.com>
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+ */
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+#include <linux/interrupt.h>
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+#include <linux/time.h>
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+#include <linux/timex.h>
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+#include <linux/clockchips.h>
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+#include <linux/clocksource.h>
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+#include <linux/types.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/irq.h>
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+
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+#include <mach/hardware.h>
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+#include <mach/irqs.h>
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+
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+/* Generic stuff */
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+#include <asm/sched_clock.h>
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+#include <asm/mach/map.h>
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+#include <asm/mach/time.h>
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+
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+#include "timer.h"
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+
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+/*
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+ * APP side special timer registers
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+ * This timer contains four timers which can fire an interrupt each.
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+ * OS (operating system) timer @ 32768 Hz
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+ * DD (device driver) timer @ 1 kHz
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+ * GP1 (general purpose 1) timer @ 1MHz
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+ * GP2 (general purpose 2) timer @ 1MHz
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+ */
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+
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+/* Reset OS Timer 32bit (-/W) */
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+#define U300_TIMER_APP_ROST (0x0000)
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+#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
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+/* Enable OS Timer 32bit (-/W) */
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+#define U300_TIMER_APP_EOST (0x0004)
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+#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
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+/* Disable OS Timer 32bit (-/W) */
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+#define U300_TIMER_APP_DOST (0x0008)
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+#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
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+/* OS Timer Mode Register 32bit (-/W) */
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+#define U300_TIMER_APP_SOSTM (0x000c)
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+#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
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+#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
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+/* OS Timer Status Register 32bit (R/-) */
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+#define U300_TIMER_APP_OSTS (0x0010)
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+#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
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+#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
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+#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
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+#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
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+#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
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+#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
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+#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
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+#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
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+#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
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+/* OS Timer Current Count Register 32bit (R/-) */
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+#define U300_TIMER_APP_OSTCC (0x0014)
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+/* OS Timer Terminal Count Register 32bit (R/W) */
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+#define U300_TIMER_APP_OSTTC (0x0018)
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+/* OS Timer Interrupt Enable Register 32bit (-/W) */
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+#define U300_TIMER_APP_OSTIE (0x001c)
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+#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
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+#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
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+/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
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+#define U300_TIMER_APP_OSTIA (0x0020)
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+#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
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+
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+/* Reset DD Timer 32bit (-/W) */
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+#define U300_TIMER_APP_RDDT (0x0040)
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+#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
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+/* Enable DD Timer 32bit (-/W) */
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+#define U300_TIMER_APP_EDDT (0x0044)
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+#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
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+/* Disable DD Timer 32bit (-/W) */
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+#define U300_TIMER_APP_DDDT (0x0048)
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+#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
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+/* DD Timer Mode Register 32bit (-/W) */
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