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@@ -142,3 +142,118 @@
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#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
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#endif /* CONFIG_PLAT_USRV */
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+
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+#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
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+#define PLD_ICUISTS_VECB_MASK (0xf000)
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+#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
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+#define PLD_ICUISTS_ISN_MASK (0x07c0)
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+#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
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+#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
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+#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
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+#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
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+#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
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+#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
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+#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
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+#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
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+#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
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+#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
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+#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
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+#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
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+#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
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+#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
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+#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
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+#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
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+#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
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+#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
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+#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
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+#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
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+#define PLD_ICUCR_IEN (0x1000)
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+#define PLD_ICUCR_IREQ (0x0100)
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+#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
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+#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
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+#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
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+#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
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+#define PLD_ICUCR_ILEVEL0 (0x0000)
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+#define PLD_ICUCR_ILEVEL1 (0x0001)
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+#define PLD_ICUCR_ILEVEL2 (0x0002)
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+#define PLD_ICUCR_ILEVEL3 (0x0003)
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+#define PLD_ICUCR_ILEVEL4 (0x0004)
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+#define PLD_ICUCR_ILEVEL5 (0x0005)
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+#define PLD_ICUCR_ILEVEL6 (0x0006)
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+#define PLD_ICUCR_ILEVEL7 (0x0007)
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+
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+/* Power Control of MMC and CF */
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+#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
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+#define PLD_CPCR_CF 0x0001
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+#define PLD_CPCR_MMC 0x0002
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+
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+/* LED Control
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+ *
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+ * 1: DIP swich side
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+ * 2: Reset switch side
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+ */
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+#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
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+#define PLD_IOLED_1_ON 0x001
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+#define PLD_IOLED_1_OFF 0x000
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+#define PLD_IOLED_2_ON 0x002
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+#define PLD_IOLED_2_OFF 0x000
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+
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+/* DIP Switch
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+ * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
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+ * 1: -
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+ * 2: -
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+ * 3: -
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+ */
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+#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
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+#define PLD_IOSWSTS_IOSW2 0x0200
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+#define PLD_IOSWSTS_IOSW1 0x0100
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+#define PLD_IOSWSTS_IOWP0 0x0001
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+
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+/* CRC */
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+#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
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+#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
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+#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
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+#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
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+#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
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+#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
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+
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+/* RTC */
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+#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
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+#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
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+#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
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+#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
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+#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
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+
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+/* SIO0 */
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+#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
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+#define PLD_ESIO0CR_TXEN 0x0001
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+#define PLD_ESIO0CR_RXEN 0x0002
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+#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
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+#define PLD_ESIO0MOD0_CTSS 0x0040
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+#define PLD_ESIO0MOD0_RTSS 0x0080
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+#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
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+#define PLD_ESIO0MOD1_LMFS 0x0010
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+#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
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+#define PLD_ESIO0STS_TEMP 0x0001
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+#define PLD_ESIO0STS_TXCP 0x0002
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+#define PLD_ESIO0STS_RXCP 0x0004
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+#define PLD_ESIO0STS_TXSC 0x0100
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+#define PLD_ESIO0STS_RXSC 0x0200
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+#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
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+#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
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+#define PLD_ESIO0INTCR_TXIEN 0x0002
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+#define PLD_ESIO0INTCR_RXCEN 0x0004
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+#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
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+#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
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+#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
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+
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+/* SIM Card */
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+#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
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+#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
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+#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
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+#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
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+#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
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+#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
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+#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
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+
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+#endif /* _M32700UT_M32700UT_PLD.H */
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苏金阳