efHeterogeneousSynchronization heterogeneousDataSynchronization.c 韩正义 commit at 2021-02-03

efHeterogeneousSynchronization/dataCalculation/heterogeneousDataSynchronization.c

@@ -757,3 +757,136 @@ marvel_print_pox_err(u64 err_sum, struct ev7_pal_io_one_port *port)
 	}
 
 	/*
+	 * POx_TRANS_SUM, if appropriate.
+	 */
+	if (err_sum & IO7__POX_ERRSUM__TRANS_SUM__MASK) 
+		marvel_print_pox_trans_sum(port->pox_trans_sum);
+
+	/*
+	 * Then TLB_ERR.
+	 */
+	if (err_sum & IO7__POX_ERRSUM__TLB_ERR) {
+		printk("%s    TLB ERROR\n", err_print_prefix);
+		marvel_print_pox_tlb_err(port->pox_tlb_err);
+	}
+
+	/*
+	 * And the single bit status errors.
+	 */
+	if (err_sum & IO7__POX_ERRSUM__AGP_REQQ_OVFL)
+		printk("%s    AGP Request Queue Overflow\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__AGP_SYNC_ERR)
+		printk("%s    AGP Sync Error\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__PCIX_DISCARD_SPL)
+		printk("%s    Discarded split completion\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__DMA_RD_TO)
+		printk("%s    DMA Read Timeout\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__CSR_NXM_RD)
+		printk("%s    CSR NXM READ\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__CSR_NXM_WR)
+		printk("%s    CSR NXM WRITE\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__DETECTED_SERR)
+		printk("%s    SERR detected\n", err_print_prefix);
+	if (err_sum & IO7__POX_ERRSUM__HUNG_BUS)
+		printk("%s    HUNG BUS detected\n", err_print_prefix);
+}
+
+#endif /* CONFIG_VERBOSE_MCHECK */
+
+static struct ev7_pal_io_subpacket *
+marvel_find_io7_with_error(struct ev7_lf_subpackets *lf_subpackets)
+{
+	struct ev7_pal_io_subpacket *io = lf_subpackets->io;
+	struct io7 *io7;
+	int i;
+
+	/*
+	 * Caller must provide the packet to fill
+	 */
+	if (!io)
+		return NULL;
+
+	/*
+	 * Fill the subpacket with the console's standard fill pattern
+	 */
+	memset(io, 0x55, sizeof(*io));
+
+	for (io7 = NULL; NULL != (io7 = marvel_next_io7(io7)); ) {
+		unsigned long err_sum = 0;
+
+		err_sum |= io7->csrs->PO7_ERROR_SUM.csr;
+		for (i = 0; i < IO7_NUM_PORTS; i++) {
+			if (!io7->ports[i].enabled)
+				continue;
+			err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr;
+		}
+
+		/*
+		 * Is there at least one error? 
+		 */
+		if (err_sum & (1UL << 63))
+			break;
+	}
+
+	/*
+	 * Did we find an IO7 with an error?
+	 */
+	if (!io7)
+		return NULL;
+
+	/*
+	 * We have an IO7 with an error. 
+	 *
+	 * Fill in the IO subpacket.
+	 */
+	io->io_asic_rev   = io7->csrs->IO_ASIC_REV.csr;
+	io->io_sys_rev    = io7->csrs->IO_SYS_REV.csr;
+	io->io7_uph       = io7->csrs->IO7_UPH.csr;
+	io->hpi_ctl       = io7->csrs->HPI_CTL.csr;
+	io->crd_ctl       = io7->csrs->CRD_CTL.csr;
+	io->hei_ctl       = io7->csrs->HEI_CTL.csr;
+	io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr;
+	io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr;
+	io->po7_crrct_sym = io7->csrs->PO7_CRRCT_SYM.csr;
+	io->po7_ugbge_sym = io7->csrs->PO7_UGBGE_SYM.csr;
+	io->po7_err_pkt0  = io7->csrs->PO7_ERR_PKT[0].csr;
+	io->po7_err_pkt1  = io7->csrs->PO7_ERR_PKT[1].csr;
+	
+	for (i = 0; i < IO7_NUM_PORTS; i++) {
+		io7_ioport_csrs *csrs = io7->ports[i].csrs;
+
+		if (!io7->ports[i].enabled)
+			continue;
+
+		io->ports[i].pox_err_sum   = csrs->POx_ERR_SUM.csr;
+		io->ports[i].pox_tlb_err   = csrs->POx_TLB_ERR.csr;
+		io->ports[i].pox_spl_cmplt = csrs->POx_SPL_COMPLT.csr;
+		io->ports[i].pox_trans_sum = csrs->POx_TRANS_SUM.csr;
+		io->ports[i].pox_first_err = csrs->POx_FIRST_ERR.csr;
+		io->ports[i].pox_mult_err  = csrs->POx_MULT_ERR.csr;
+		io->ports[i].pox_dm_source = csrs->POx_DM_SOURCE.csr;
+		io->ports[i].pox_dm_dest   = csrs->POx_DM_DEST.csr;
+		io->ports[i].pox_dm_size   = csrs->POx_DM_SIZE.csr;
+		io->ports[i].pox_dm_ctrl   = csrs->POx_DM_CTRL.csr;
+
+		/*
+		 * Ack this port's errors, if any. POx_ERR_SUM must be last.
+		 *
+		 * Most of the error registers get cleared and unlocked when
+		 * the associated bits in POx_ERR_SUM are cleared (by writing
+		 * 1). POx_TLB_ERR is an exception and must be explicitly 
+		 * cleared.
+		 */
+		csrs->POx_TLB_ERR.csr = io->ports[i].pox_tlb_err;
+		csrs->POx_ERR_SUM.csr =	io->ports[i].pox_err_sum;
+		mb();
+		csrs->POx_ERR_SUM.csr;		
+	}
+
+	/*
+	 * Ack any port 7 error(s).
+	 */
+	io7->csrs->PO7_ERROR_SUM.csr = io->po7_error_sum;
+	mb();
+	io7->csrs->PO7_ERROR_SUM.csr;
+