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@@ -1082,3 +1082,119 @@
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#define ERR_DET 0x4000 /* Error Detected Indicator */
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#define ERR_DET 0x4000 /* Error Detected Indicator */
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#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
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#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
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+
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+/* ******************* PIN CONTROL REGISTER MASKS ************************/
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+/* PORT_MUX Masks */
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+#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
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+#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
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+#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
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+
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+#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
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+#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
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+#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
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+#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
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+
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+#define PFDE 0x0008 /* Port F DMA Request Enable */
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+#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
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+#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
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+
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+#define PFTE 0x0010 /* Port F Timer Enable */
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+#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
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+#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
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+
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+#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
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+#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
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+#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
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+
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+#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
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+#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
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+#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
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+
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+#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
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+#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
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+#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
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+
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+#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
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+#define PFFE_TIMER 0x0000 /* Enable TMR2 */
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+#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
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+
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+#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
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+#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
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+#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
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+
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+#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
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+#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
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+#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
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+
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+#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
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+#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
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+#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
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+
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+/* entry addresses of the user-callable Boot ROM functions */
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+
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+#define _BOOTROM_RESET 0xEF000000
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+#define _BOOTROM_FINAL_INIT 0xEF000002
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+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
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+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
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+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
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+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
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+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
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+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
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+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
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+
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+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
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+#define PGDE_UART PFDE_UART
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+#define PGDE_DMA PFDE_DMA
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+#define CKELOW SCKELOW
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+
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+/* HOST Port Registers */
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+
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+#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
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+#define HOST_STATUS 0xffc03404 /* HOST Status Register */
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+#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
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+
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+/* Counter Registers */
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+
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+#define CNT_CONFIG 0xffc03500 /* Configuration Register */
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+#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
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+#define CNT_STATUS 0xffc03508 /* Status Register */
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+#define CNT_COMMAND 0xffc0350c /* Command Register */
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+#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
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+#define CNT_COUNTER 0xffc03514 /* Counter Register */
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+#define CNT_MAX 0xffc03518 /* Maximal Count Register */
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+#define CNT_MIN 0xffc0351c /* Minimal Count Register */
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+
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+/* OTP/FUSE Registers */
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+
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+#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
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+#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
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+#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
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+#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
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+
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+/* Security Registers */
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+
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+#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
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+#define SECURE_CONTROL 0xffc03624 /* Secure Control */
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+#define SECURE_STATUS 0xffc03628 /* Secure Status */
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+
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+/* OTP Read/Write Data Buffer Registers */
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+
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+#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+
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+/* Motor Control PWM Registers */
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+
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+#define PWM_CTRL 0xffc03700 /* PWM Control Register */
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+#define PWM_STAT 0xffc03704 /* PWM Status Register */
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+#define PWM_TM 0xffc03708 /* PWM Period Register */
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+#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
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+#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
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+#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
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+#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
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+#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
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+#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
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+#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
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+#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
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+#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
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