|
@@ -1300,3 +1300,69 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio6_dbclk" },
|
|
{ .role = "dbclk", .clk = "gpio6_dbclk" },
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct omap_hwmod omap44xx_gpio6_hwmod = {
|
|
|
|
+ .name = "gpio6",
|
|
|
|
+ .class = &omap44xx_gpio_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4_per_clkdm",
|
|
|
|
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
|
|
+ .mpu_irqs = omap44xx_gpio6_irqs,
|
|
|
|
+ .main_clk = "gpio6_ick",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
|
|
|
|
+ .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_HWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+ .opt_clks = gpio6_opt_clks,
|
|
|
|
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
|
|
|
|
+ .dev_attr = &gpio_dev_attr,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * 'gpmc' class
|
|
|
|
+ * general purpose memory controller
|
|
|
|
+ */
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
|
|
|
|
+ .rev_offs = 0x0000,
|
|
|
|
+ .sysc_offs = 0x0010,
|
|
|
|
+ .syss_offs = 0x0014,
|
|
|
|
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
|
|
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
|
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
|
|
|
|
+ .name = "gpmc",
|
|
|
|
+ .sysc = &omap44xx_gpmc_sysc,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* gpmc */
|
|
|
|
+static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
|
|
|
|
+ { .irq = 20 + OMAP44XX_IRQ_GIC_START },
|
|
|
|
+ { .irq = -1 }
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
|
|
|
|
+ { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
|
|
|
|
+ { .dma_req = -1 }
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod omap44xx_gpmc_hwmod = {
|
|
|
|
+ .name = "gpmc",
|
|
|
|
+ .class = &omap44xx_gpmc_hwmod_class,
|
|
|
|
+ .clkdm_name = "l3_2_clkdm",
|
|
|
|
+ /*
|
|
|
|
+ * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
|
|
|
|
+ * block. It is not being added due to any known bugs with
|
|
|
|
+ * resetting the GPMC IP block, but rather because any timings
|
|
|
|
+ * set by the bootloader are not being correctly programmed by
|
|
|
|
+ * the kernel from the board file or DT data.
|
|
|
|
+ * HWMOD_INIT_NO_RESET should be removed ASAP.
|
|
|
|
+ */
|
|
|
|
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
|
|
|
+ .mpu_irqs = omap44xx_gpmc_irqs,
|
|
|
|
+ .sdma_reqs = omap44xx_gpmc_sdma_reqs,
|
|
|
|
+ .prcm = {
|