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@@ -0,0 +1,69 @@
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+/*
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+ * Copyright (C) 2009 Nokia
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+ * Copyright (C) 2009 Texas Instruments
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU
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+
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+#define OMAP2430_MUX(mode0, mux_value) \
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+{ \
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+ .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \
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+ .value = (mux_value), \
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+}
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+
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+/*
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+ * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
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+ *
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+ * Extracted from the TRM. Add 0x49002030 to these values to get the
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+ * absolute addresses. The name in the macro is the mode-0 name of
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+ * the pin. NOTE: These registers are 8-bits wide.
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+ *
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+ * Note that these defines use SDMMC instead of MMC for compatibility
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+ * with signal names used in 3630.
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+ */
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+#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d
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+#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e
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+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f
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+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010
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+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011
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+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012
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+#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016
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+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017
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+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a
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+#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022
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+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023
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+#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024
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+#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025
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+#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026
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+#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027
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+#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028
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+#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029
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