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@@ -0,0 +1,71 @@
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+/*
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+ * Copyright 2007-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef _CDEF_BF522_H
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+#define _CDEF_BF522_H
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+
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+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
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+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
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+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
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+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
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+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
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+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
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+#define bfin_read_CHIPID() bfin_read32(CHIPID)
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+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
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+
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+
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+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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+#define bfin_read_SWRST() bfin_read16(SWRST)
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+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
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+#define bfin_read_SYSCR() bfin_read16(SYSCR)
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+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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+
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+#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
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+#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
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+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
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+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
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+#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
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+#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
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+
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+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
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+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
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+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
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+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
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+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
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+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
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+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
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+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
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+
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+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
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+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
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+#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
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+#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
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+
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+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
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+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
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+#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
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+#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
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+
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+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
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+
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+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
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+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
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+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
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+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
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+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
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+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
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+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
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+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
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+#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
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+#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
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+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
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+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
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+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
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+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
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+
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