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@@ -1646,3 +1646,178 @@
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/* Bit masks for EBIU_AMBCTL0 */
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#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
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+#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
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+#define B0TT 0xc /* Bank 0 transition time */
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+#define B0ST 0x30 /* Bank 0 Setup time */
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+#define B0HT 0xc0 /* Bank 0 Hold time */
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+#define B0RAT 0xf00 /* Bank 0 Read access time */
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+#define B0WAT 0xf000 /* Bank 0 write access time */
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+#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
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+#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
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+#define B1TT 0xc0000 /* Bank 1 transition time */
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+#define B1ST 0x300000 /* Bank 1 Setup time */
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+#define B1HT 0xc00000 /* Bank 1 Hold time */
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+#define B1RAT 0xf000000 /* Bank 1 Read access time */
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+#define B1WAT 0xf0000000 /* Bank 1 write access time */
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+
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+/* Bit masks for EBIU_AMBCTL1 */
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+
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+#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
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+#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
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+#define B2TT 0xc /* Bank 2 transition time */
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+#define B2ST 0x30 /* Bank 2 Setup time */
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+#define B2HT 0xc0 /* Bank 2 Hold time */
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+#define B2RAT 0xf00 /* Bank 2 Read access time */
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+#define B2WAT 0xf000 /* Bank 2 write access time */
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+#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
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+#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
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+#define B3TT 0xc0000 /* Bank 3 transition time */
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+#define B3ST 0x300000 /* Bank 3 Setup time */
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+#define B3HT 0xc00000 /* Bank 3 Hold time */
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+#define B3RAT 0xf000000 /* Bank 3 Read access time */
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+#define B3WAT 0xf0000000 /* Bank 3 write access time */
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+
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+/* Bit masks for EBIU_MBSCTL */
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+
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+#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
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+#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
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+#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
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+#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
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+
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+/* Bit masks for EBIU_MODE */
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+
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+#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
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+#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
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+#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
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+#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
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+
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+/* Bit masks for EBIU_FCTL */
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+
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+#define TESTSETLOCK 0x1 /* Test set lock */
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+#define BCLK 0x6 /* Burst clock frequency */
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+#define PGWS 0x38 /* Page wait states */
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+#define PGSZ 0x40 /* Page size */
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+#define RDDL 0x380 /* Read data delay */
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+
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+/* Bit masks for EBIU_ARBSTAT */
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+
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+#define ARBSTAT 0x1 /* Arbitration status */
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+#define BGSTAT 0x2 /* Bus grant status */
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+
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+/* Bit masks for EBIU_DDRCTL0 */
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+
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+#define TREFI 0x3fff /* Refresh Interval */
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+#define TRFC 0x3c000 /* Auto-refresh command period */
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+#define TRP 0x3c0000 /* Pre charge-to-active command period */
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+#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
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+#define TRC 0x3c000000 /* Active-to-active time */
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+#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
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+#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
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+#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
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+#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
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+#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
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+
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+/* Bit masks for EBIU_DDRCTL1 */
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+
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+#define TRCD 0xf /* Active-to-Read/write delay */
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+#define TMRD 0xf0 /* Mode register set to active */
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+#define TWR 0x300 /* Write Recovery time */
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+#define DDRDATWIDTH 0x3000 /* DDR data width */
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+#define EXTBANKS 0xc000 /* External banks */
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+#define DDRDEVWIDTH 0x30000 /* DDR device width */
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+#define DDRDEVSIZE 0xc0000 /* DDR device size */
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+#define TWTR 0xf0000000 /* Write-to-read delay */
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+#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
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+#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
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+#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
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+#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
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+#define DDR_DATWIDTH 0x2000 /* DDR data width */
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+#define EXTBANK_1 0 /* 1 external bank */
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+#define EXTBANK_2 0x4000 /* 2 external banks */
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+#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
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+#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
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+#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
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+#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
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+#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
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+#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
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+#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
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+
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+/* Bit masks for EBIU_DDRCTL2 */
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+
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+#define BURSTLENGTH 0x7 /* Burst length */
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+#define CASLATENCY 0x70 /* CAS latency */
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+#define DLLRESET 0x100 /* DLL Reset */
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+#define REGE 0x1000 /* Register mode enable */
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+#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
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+#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
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+#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
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+#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
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+
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+/* Bit masks for EBIU_DDRCTL3 */
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+
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+#define PASR 0x7 /* Partial array self-refresh */
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+
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+/* Bit masks for EBIU_DDRQUE */
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+
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+#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
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+#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
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+#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
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+#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
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+#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
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+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
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+#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
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+
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+/* Bit masks for EBIU_ERRMST */
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+
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+#define DEB1_ERROR 0x1 /* DEB1 Error */
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+#define DEB2_ERROR 0x2 /* DEB2 Error */
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+#define DEB3_ERROR 0x4 /* DEB3 Error */
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+#define CORE_ERROR 0x8 /* Core error */
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+#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
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+#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
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+#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
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+#define CORE_MERROR 0x80 /* Core Error (2nd) */
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+
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+/* Bit masks for EBIU_RSTCTL */
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+
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+#define DDRSRESET 0x1 /* DDR soft reset */
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+#define PFTCHSRESET 0x4 /* DDR prefetch reset */
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+#define SRREQ 0x8 /* Self-refresh request */
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+#define SRACK 0x10 /* Self-refresh acknowledge */
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+#define MDDRENABLE 0x20 /* Mobile DDR enable */
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+
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+/* Bit masks for EBIU_DDRMCEN */
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+
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+#define B0WCENABLE 0x1 /* Bank 0 write count enable */
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+#define B1WCENABLE 0x2 /* Bank 1 write count enable */
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+#define B2WCENABLE 0x4 /* Bank 2 write count enable */
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+#define B3WCENABLE 0x8 /* Bank 3 write count enable */
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+#define B4WCENABLE 0x10 /* Bank 4 write count enable */
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+#define B5WCENABLE 0x20 /* Bank 5 write count enable */
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+#define B6WCENABLE 0x40 /* Bank 6 write count enable */
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+#define B7WCENABLE 0x80 /* Bank 7 write count enable */
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+#define B0RCENABLE 0x100 /* Bank 0 read count enable */
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+#define B1RCENABLE 0x200 /* Bank 1 read count enable */
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+#define B2RCENABLE 0x400 /* Bank 2 read count enable */
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+#define B3RCENABLE 0x800 /* Bank 3 read count enable */
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+#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
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+#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
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+#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
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+#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
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+#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
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+#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
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+#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
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+#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
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+#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
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+#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
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+#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
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+#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
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+
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+/* Bit masks for EBIU_DDRMCCL */
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+
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+#define CB0WCOUNT 0x1 /* Clear write count 0 */
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+#define CB1WCOUNT 0x2 /* Clear write count 1 */
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+#define CB2WCOUNT 0x4 /* Clear write count 2 */
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+#define CB3WCOUNT 0x8 /* Clear write count 3 */
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+#define CB4WCOUNT 0x10 /* Clear write count 4 */
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+#define CB5WCOUNT 0x20 /* Clear write count 5 */
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吉超博