|  | @@ -287,3 +287,85 @@ static const struct clksel_rate dsp_fck_core_rates[] = {
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				|  |  |  	{ .div = 0 }
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				|  |  |  };
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				|  |  |  
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				|  |  | +static const struct clksel dsp_fck_clksel[] = {
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				|  |  | +	{ .parent = &core_ck, .rates = dsp_fck_core_rates },
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				|  |  | +	{ .parent = NULL },
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const char *dsp_fck_parent_names[] = {
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				|  |  | +	"core_ck",
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const struct clk_ops dsp_fck_ops = {
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				|  |  | +	.init		= &omap2_init_clk_clkdm,
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				|  |  | +	.enable		= &omap2_dflt_clk_enable,
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				|  |  | +	.disable	= &omap2_dflt_clk_disable,
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				|  |  | +	.is_enabled	= &omap2_dflt_clk_is_enabled,
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				|  |  | +	.recalc_rate	= &omap2_clksel_recalc,
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				|  |  | +	.set_rate	= &omap2_clksel_set_rate,
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				|  |  | +	.round_rate	= &omap2_clksel_round_rate,
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				|  |  | +};
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				|  |  | +
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				|  |  | +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
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				|  |  | +			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
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				|  |  | +			 OMAP24XX_CLKSEL_DSP_MASK,
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				|  |  | +			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
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				|  |  | +			 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
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				|  |  | +			 dsp_fck_parent_names, dsp_fck_ops);
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				|  |  | +
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				|  |  | +static const struct clksel dsp_ick_clksel[] = {
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				|  |  | +	{ .parent = &dsp_fck, .rates = dsp_ick_rates },
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				|  |  | +	{ .parent = NULL },
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const char *dsp_ick_parent_names[] = {
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				|  |  | +	"dsp_fck",
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				|  |  | +};
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				|  |  | +
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				|  |  | +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
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				|  |  | +			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
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				|  |  | +			 OMAP24XX_CLKSEL_DSP_IF_MASK,
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				|  |  | +			 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
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				|  |  | +			 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
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				|  |  | +			 dsp_ick_parent_names, dsp_fck_ops);
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				|  |  | +
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				|  |  | +static const struct clksel_rate dss1_fck_sys_rates[] = {
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				|  |  | +	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 0 }
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const struct clksel_rate dss1_fck_core_rates[] = {
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				|  |  | +	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 5, .val = 5, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
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				|  |  | +	{ .div = 0 }
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const struct clksel dss1_fck_clksel[] = {
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				|  |  | +	{ .parent = &sys_ck, .rates = dss1_fck_sys_rates },
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				|  |  | +	{ .parent = &core_ck, .rates = dss1_fck_core_rates },
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				|  |  | +	{ .parent = NULL },
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				|  |  | +};
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				|  |  | +
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				|  |  | +static const char *dss1_fck_parent_names[] = {
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				|  |  | +	"sys_ck", "core_ck",
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct clk dss1_fck;
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				|  |  | +
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				|  |  | +static const struct clk_ops dss1_fck_ops = {
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				|  |  | +	.init		= &omap2_init_clk_clkdm,
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				|  |  | +	.enable		= &omap2_dflt_clk_enable,
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				|  |  | +	.disable	= &omap2_dflt_clk_disable,
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				|  |  | +	.is_enabled	= &omap2_dflt_clk_is_enabled,
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				|  |  | +	.recalc_rate	= &omap2_clksel_recalc,
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				|  |  | +	.get_parent	= &omap2_clksel_find_parent_index,
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				|  |  | +	.set_parent	= &omap2_clksel_set_parent,
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				|  |  | +};
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