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@@ -392,3 +392,30 @@ static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
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{S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
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{S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
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{S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
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+ {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
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+ {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
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+ {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
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+ {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
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+ {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
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+ {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
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+ {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
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+ {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
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+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
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+ {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
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+ {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
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+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
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+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
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+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
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+ {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
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+ {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
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+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
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+ {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
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+ {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
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+ {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
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+ {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
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+ {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
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+ {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
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+ {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
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+ {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
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+ {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
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+ {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
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朱涛