| 
					
				 | 
			
			
				@@ -441,3 +441,37 @@ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS	_BIT(8) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS	_BIT(7) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS	_BIT(6) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN		_BIT(5) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n)	((n) & 0xF) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * clkpwr_macclk_ctrl register definitions 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS	0x00 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS	0x08 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS	0x18 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK		0x18 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN	_BIT(2) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN	_BIT(1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN	_BIT(0) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * clkpwr_test_clk_sel register definitions 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK	(0x0 << 5) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC		(0x1 << 5) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC	(0x2 << 5) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK	(0x3 << 5) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN	_BIT(4) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK	(0x0 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK	(0x1 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK	(0x2 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC	(0x5 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397	(0x7 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK	(0x7 << 1) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN	_BIT(0) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ * clkpwr_sw_int register definitions 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define LPC32XX_CLKPWR_SW_INT(n)		(_BIT(0) | (((n) & 0x7F) << 1)) 
			 |