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@@ -585,3 +585,97 @@
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#define CHIPID_VERSION 0xF0000000
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#define CHIPID_FAMILY 0x0FFFF000
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#define CHIPID_MANUFACTURE 0x00000FFE
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+
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+/* SWRST Masks */
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+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
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+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
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+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
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+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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+
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+/* SYSCR Masks */
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+#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
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+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
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+
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+
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+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
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+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
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+
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+#if 0
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+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
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+
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+#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
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+#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
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+#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
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+#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
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+#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
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+#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
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+#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
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+
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+#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
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+#define IRQ_TWI 0x00000200 /* TWI Interrupt */
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+#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
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+#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
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+#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
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+#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
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+#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
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+#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
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+
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+#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
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+#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
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+#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
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+#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
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+#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
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+#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
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+#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
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+#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
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+#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
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+#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
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+
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+#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
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+#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
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+#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
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+#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
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+#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
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+#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
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+#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
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+#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
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+#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
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+#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
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+#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
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+#endif
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+
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+/* SIC_IAR0 Macros */
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+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
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+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
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+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
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+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
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+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
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+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
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+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
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+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
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+
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+/* SIC_IAR1 Macros */
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+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
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+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
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+#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
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+#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
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+#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
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+#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
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+#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
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+#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
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+
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+/* SIC_IAR2 Macros */
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+#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
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+#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
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+#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
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+#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
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+#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
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+#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
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+#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
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+#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
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+
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+/* SIC_IAR3 Macros */
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+#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
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+#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
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+#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
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