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@@ -1198,3 +1198,102 @@
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#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
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#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
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#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
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+#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
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+#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
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+#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
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+#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
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+#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
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+#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
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+#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
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+#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
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+#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
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+#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
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+#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
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+#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
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+#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
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+#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
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+#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
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+#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
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+#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
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+#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
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+#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
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+#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
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+#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
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+#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
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+#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
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+#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
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+#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
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+#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
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+#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
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+#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
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+#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
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+#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
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+#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
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+#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
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+#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
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+#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
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+#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
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+#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
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+#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
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+#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
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+#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
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+
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+#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
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+#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
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+#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
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+#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
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+#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
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+#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
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+#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
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+#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
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+#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
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+#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
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+#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
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+#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
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+#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
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+#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
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+#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
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+#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
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+#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
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+#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
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+#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
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+#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
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+#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
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+#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
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+#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
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+#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
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+#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
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+#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
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+#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
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+#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
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+#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
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+#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
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+#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
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+#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
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+#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
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+#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
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+#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
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+#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
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+#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
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+#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
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+#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
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+#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
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+#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
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+#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
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+#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
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+#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
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+
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+/* ********************** SDRAM CONTROLLER MASKS **********************************************/
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+/* EBIU_SDGCTL Masks */
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+#define SCTLE 0x00000001 /* Enable SDRAM Signals */
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+#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
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+#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
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+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
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+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
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+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
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+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
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+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
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+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
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+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
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+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
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+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
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李欣儒