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+/* linux/arch/arm/mach-exynos/include/mach/map.h
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+ *
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+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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+ * http://www.samsung.com/
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+ *
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+ * EXYNOS4 - Memory map definitions
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+*/
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+
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+#ifndef __ASM_ARCH_MAP_H
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+#define __ASM_ARCH_MAP_H __FILE__
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+
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+#include <plat/map-base.h>
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+
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+/*
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+ * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
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+ * So need to define it, and here is to avoid redefinition warning.
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+ */
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+#define S3C_UART_OFFSET (0x10000)
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+
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+#include <plat/map-s5p.h>
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+
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+#define EXYNOS4_PA_SYSRAM0 0x02025000
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+#define EXYNOS4_PA_SYSRAM1 0x02020000
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+#define EXYNOS5_PA_SYSRAM 0x02020000
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+
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+#define EXYNOS4_PA_FIMC0 0x11800000
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+#define EXYNOS4_PA_FIMC1 0x11810000
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+#define EXYNOS4_PA_FIMC2 0x11820000
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+#define EXYNOS4_PA_FIMC3 0x11830000
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+
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+#define EXYNOS4_PA_JPEG 0x11840000
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+
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+/* x = 0...1 */
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+#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
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+
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+#define EXYNOS4_PA_G2D 0x12800000
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+
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+#define EXYNOS4_PA_I2S0 0x03830000
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+#define EXYNOS4_PA_I2S1 0xE3100000
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+#define EXYNOS4_PA_I2S2 0xE2A00000
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+
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+#define EXYNOS4_PA_PCM0 0x03840000
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+#define EXYNOS4_PA_PCM1 0x13980000
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+#define EXYNOS4_PA_PCM2 0x13990000
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+
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+#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
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+
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+#define EXYNOS4_PA_ONENAND 0x0C000000
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+#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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+
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+#define EXYNOS_PA_CHIPID 0x10000000
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+#define EXYNOS5440_PA_CHIPID 0x00160000
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+
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+#define EXYNOS4_PA_SYSCON 0x10010000
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+#define EXYNOS5_PA_SYSCON 0x10050100
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+
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+#define EXYNOS4_PA_PMU 0x10020000
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+#define EXYNOS5_PA_PMU 0x10040000
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+
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+#define EXYNOS4_PA_CMU 0x10030000
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+#define EXYNOS5_PA_CMU 0x10010000
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+
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+#define EXYNOS4_PA_SYSTIMER 0x10050000
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+#define EXYNOS5_PA_SYSTIMER 0x101C0000
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+
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+#define EXYNOS4_PA_WATCHDOG 0x10060000
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+#define EXYNOS5_PA_WATCHDOG 0x101D0000
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+
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+#define EXYNOS4_PA_RTC 0x10070000
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+
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+#define EXYNOS4_PA_KEYPAD 0x100A0000
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+
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+#define EXYNOS4_PA_DMC0 0x10400000
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+#define EXYNOS4_PA_DMC1 0x10410000
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+
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+#define EXYNOS4_PA_COMBINER 0x10440000
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+#define EXYNOS5_PA_COMBINER 0x10440000
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+
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+#define EXYNOS4_PA_GIC_CPU 0x10480000
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+#define EXYNOS4_PA_GIC_DIST 0x10490000
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+#define EXYNOS5_PA_GIC_CPU 0x10482000
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+#define EXYNOS5_PA_GIC_DIST 0x10481000
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+
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+#define EXYNOS4_PA_COREPERI 0x10500000
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+#define EXYNOS4_PA_TWD 0x10500600
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+#define EXYNOS4_PA_L2CC 0x10502000
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+
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+#define EXYNOS4_PA_TMU 0x100C0000
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+
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+#define EXYNOS4_PA_MDMA0 0x10810000
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+#define EXYNOS4_PA_MDMA1 0x12850000
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+#define EXYNOS4_PA_S_MDMA1 0x12840000
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+#define EXYNOS4_PA_PDMA0 0x12680000
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+#define EXYNOS4_PA_PDMA1 0x12690000
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+#define EXYNOS5_PA_MDMA0 0x10800000
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+#define EXYNOS5_PA_MDMA1 0x11C10000
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+#define EXYNOS5_PA_PDMA0 0x121A0000
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+#define EXYNOS5_PA_PDMA1 0x121B0000
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+
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+#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
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+#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
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+#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
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+#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
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+#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
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+#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
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+#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
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+#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
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+#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
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+#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
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+#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
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+#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
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+#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
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+#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
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+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
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+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
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+#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
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+#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
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+#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
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+#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
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+#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
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+#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
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+#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
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+
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+#define EXYNOS5_PA_GSC0 0x13E00000
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+#define EXYNOS5_PA_GSC1 0x13E10000
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+#define EXYNOS5_PA_GSC2 0x13E20000
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+#define EXYNOS5_PA_GSC3 0x13E30000
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+
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+#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
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+#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
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+#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
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+#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
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+#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
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+#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
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+#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
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