efElectricAgingTrendMining memoryOperation.h 岳彩东 commit at 2020-11-18

efElectricAgingTrendMining/dataSharedMemory/memoryOperation.h

@@ -1258,3 +1258,191 @@
 #define OMAP4430_TESLA_L2_RETSTATE_MASK					(1 << 9)
 
 /* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L2_STATEST_SHIFT					6
+#define OMAP4430_TESLA_L2_STATEST_MASK					(0x3 << 6)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_TIMEOUT_SHIFT						0
+#define OMAP4430_TIMEOUT_MASK						(0xffff << 0)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_TIMEOUTEN_SHIFT					3
+#define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_TRANSITION_EN_SHIFT					8
+#define OMAP4430_TRANSITION_EN_MASK					(1 << 8)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_TRANSITION_ST_SHIFT					8
+#define OMAP4430_TRANSITION_ST_MASK					(1 << 8)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_VALID_SHIFT						24
+#define OMAP4430_VALID_MASK						(1 << 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_BYPASSACK_EN_SHIFT					14
+#define OMAP4430_VC_BYPASSACK_EN_MASK					(1 << 14)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_BYPASSACK_ST_SHIFT					14
+#define OMAP4430_VC_BYPASSACK_ST_MASK					(1 << 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_CORE_VPACK_EN_SHIFT					22
+#define OMAP4430_VC_CORE_VPACK_EN_MASK					(1 << 22)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_CORE_VPACK_ST_SHIFT					22
+#define OMAP4430_VC_CORE_VPACK_ST_MASK					(1 << 22)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_IVA_VPACK_EN_SHIFT					30
+#define OMAP4430_VC_IVA_VPACK_EN_MASK					(1 << 30)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_IVA_VPACK_ST_SHIFT					30
+#define OMAP4430_VC_IVA_VPACK_ST_MASK					(1 << 30)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_EN_SHIFT					6
+#define OMAP4430_VC_MPU_VPACK_EN_MASK					(1 << 6)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_ST_SHIFT					6
+#define OMAP4430_VC_MPU_VPACK_ST_MASK					(1 << 6)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_RAERR_EN_SHIFT					12
+#define OMAP4430_VC_RAERR_EN_MASK					(1 << 12)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_RAERR_ST_SHIFT					12
+#define OMAP4430_VC_RAERR_ST_MASK					(1 << 12)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_SAERR_EN_SHIFT					11
+#define OMAP4430_VC_SAERR_EN_MASK					(1 << 11)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_SAERR_ST_SHIFT					11
+#define OMAP4430_VC_SAERR_ST_MASK					(1 << 11)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_TOERR_EN_SHIFT					13
+#define OMAP4430_VC_TOERR_EN_MASK					(1 << 13)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_TOERR_ST_SHIFT					13
+#define OMAP4430_VC_TOERR_ST_MASK					(1 << 13)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMAX_SHIFT						24
+#define OMAP4430_VDDMAX_MASK						(0xff << 24)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMIN_SHIFT						16
+#define OMAP4430_VDDMIN_MASK						(0xff << 16)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT				12
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK				(1 << 12)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK				(1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT				14
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK				(1 << 14)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_PRESENCE_SHIFT					9
+#define OMAP4430_VDD_IVA_PRESENCE_MASK					(1 << 9)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK				(1 << 7)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT				13
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK				(1 << 13)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_PRESENCE_SHIFT					8
+#define OMAP4430_VDD_MPU_PRESENCE_MASK					(1 << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK				(1 << 6)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT					4
+#define OMAP4430_VFSM_RA_ERR_CORE_MASK					(1 << 4)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT					12
+#define OMAP4430_VFSM_RA_ERR_IVA_MASK					(1 << 12)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT					20
+#define OMAP4430_VFSM_RA_ERR_MPU_MASK					(1 << 20)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT					3
+#define OMAP4430_VFSM_SA_ERR_CORE_MASK					(1 << 3)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT					11
+#define OMAP4430_VFSM_SA_ERR_IVA_MASK					(1 << 11)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT					19
+#define OMAP4430_VFSM_SA_ERR_MPU_MASK					(1 << 19)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT				5
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK				(1 << 5)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT				13
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK				(1 << 13)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT				21
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK				(1 << 21)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT					0
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT					8
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT					16
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_VPENABLE_SHIFT						0
+#define OMAP4430_VPENABLE_MASK						(1 << 0)
+
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP4430_VPINIDLE_SHIFT						0
+#define OMAP4430_VPINIDLE_MASK						(1 << 0)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP4430_VPVOLTAGE_SHIFT					0
+#define OMAP4430_VPVOLTAGE_MASK						(0xff << 0)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT				20
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK				(1 << 20)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT				20
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK				(1 << 20)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */