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@@ -0,0 +1,38 @@
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+/*
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+ * Copyright 2007-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the Clear BSD license or the GPL-2 (or later)
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+ */
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+
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+#ifndef _DEF_BF54X_H
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+#define _DEF_BF54X_H
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+
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+
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+/* ************************************************************** */
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+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
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+/* ************************************************************** */
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+
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+/* PLL Registers */
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+
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+#define PLL_CTL 0xffc00000 /* PLL Control Register */
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+#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
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+#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
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+#define PLL_STAT 0xffc0000c /* PLL Status Register */
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+#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
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+
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+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
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+
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+#define CHIPID 0xffc00014
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+/* CHIPID Masks */
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+#define CHIPID_VERSION 0xF0000000
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+#define CHIPID_FAMILY 0x0FFFF000
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+#define CHIPID_MANUFACTURE 0x00000FFE
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+
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+/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
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+
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+#define SWRST 0xffc00100 /* Software Reset Register */
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+#define SYSCR 0xffc00104 /* System Configuration register */
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+
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+/* SIC Registers */
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+
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+#define SIC_RVECT 0xffc00108
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