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@@ -937,3 +937,157 @@ static inline void configure_usart0_pins(unsigned pins)
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if (pins & ATMEL_UART_RTS)
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at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
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+ if (pins & ATMEL_UART_CTS)
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+ at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
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+}
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+
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+static struct resource uart1_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9261_BASE_US1,
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+ .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
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+ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct atmel_uart_data uart1_data = {
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+ .use_dma_tx = 1,
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+ .use_dma_rx = 1,
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+};
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+
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+static u64 uart1_dmamask = DMA_BIT_MASK(32);
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+
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+static struct platform_device at91sam9261_uart1_device = {
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+ .name = "atmel_usart",
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+ .id = 2,
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+ .dev = {
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+ .dma_mask = &uart1_dmamask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = &uart1_data,
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+ },
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+ .resource = uart1_resources,
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+ .num_resources = ARRAY_SIZE(uart1_resources),
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+};
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+
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+static inline void configure_usart1_pins(unsigned pins)
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+{
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+ at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
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+ at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
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+
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+ if (pins & ATMEL_UART_RTS)
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+ at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
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+ if (pins & ATMEL_UART_CTS)
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+ at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
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+}
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+
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+static struct resource uart2_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9261_BASE_US2,
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+ .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
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+ .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct atmel_uart_data uart2_data = {
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+ .use_dma_tx = 1,
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+ .use_dma_rx = 1,
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+};
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+
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+static u64 uart2_dmamask = DMA_BIT_MASK(32);
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+
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+static struct platform_device at91sam9261_uart2_device = {
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+ .name = "atmel_usart",
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+ .id = 3,
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+ .dev = {
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+ .dma_mask = &uart2_dmamask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = &uart2_data,
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+ },
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+ .resource = uart2_resources,
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+ .num_resources = ARRAY_SIZE(uart2_resources),
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+};
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+
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+static inline void configure_usart2_pins(unsigned pins)
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+{
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+ at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
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+ at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
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+
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+ if (pins & ATMEL_UART_RTS)
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+ at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
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+ if (pins & ATMEL_UART_CTS)
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+ at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
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+}
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+
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+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
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+
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+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
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+{
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+ struct platform_device *pdev;
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+ struct atmel_uart_data *pdata;
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+
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+ switch (id) {
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+ case 0: /* DBGU */
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+ pdev = &at91sam9261_dbgu_device;
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+ configure_dbgu_pins();
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+ break;
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+ case AT91SAM9261_ID_US0:
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+ pdev = &at91sam9261_uart0_device;
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+ configure_usart0_pins(pins);
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+ break;
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+ case AT91SAM9261_ID_US1:
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+ pdev = &at91sam9261_uart1_device;
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+ configure_usart1_pins(pins);
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+ break;
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+ case AT91SAM9261_ID_US2:
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+ pdev = &at91sam9261_uart2_device;
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+ configure_usart2_pins(pins);
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+ break;
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+ default:
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+ return;
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+ }
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+ pdata = pdev->dev.platform_data;
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+ pdata->num = portnr; /* update to mapped ID */
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+
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+ if (portnr < ATMEL_MAX_UART)
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+ at91_uarts[portnr] = pdev;
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+}
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+
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+void __init at91_add_device_serial(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ATMEL_MAX_UART; i++) {
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+ if (at91_uarts[i])
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+ platform_device_register(at91_uarts[i]);
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+ }
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+}
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+#else
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+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
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+void __init at91_add_device_serial(void) {}
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+#endif
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+
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+
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+/* -------------------------------------------------------------------- */
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+
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+/*
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+ * These devices are always present and don't need any board-specific
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+ * setup.
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+ */
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+static int __init at91_add_standard_devices(void)
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+{
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+ at91_add_device_rtt();
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+ at91_add_device_watchdog();
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+ at91_add_device_tc();
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+ return 0;
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+}
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+
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+arch_initcall(at91_add_standard_devices);
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