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+/*
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+ * arch/arm/mach-at91/at91rm9200.c
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+ *
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+ * Copyright (C) 2005 SAN People
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ */
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+
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+#include <linux/module.h>
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+
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+#include <asm/irq.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/map.h>
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+#include <asm/system_misc.h>
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+#include <mach/at91rm9200.h>
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+#include <mach/at91_pmc.h>
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+#include <mach/at91_st.h>
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+#include <mach/cpu.h>
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+
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+#include "at91_aic.h"
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+#include "soc.h"
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+#include "generic.h"
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+#include "clock.h"
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+#include "sam9_smc.h"
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+
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+/* --------------------------------------------------------------------
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+ * Clocks
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+ * -------------------------------------------------------------------- */
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+
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+/*
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+ * The peripheral clocks.
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+ */
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+static struct clk udc_clk = {
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+ .name = "udc_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_UDP,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk ohci_clk = {
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+ .name = "ohci_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_UHP,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk ether_clk = {
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+ .name = "ether_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_EMAC,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk mmc_clk = {
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+ .name = "mci_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_MCI,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk twi_clk = {
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+ .name = "twi_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TWI,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk usart0_clk = {
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+ .name = "usart0_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_US0,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk usart1_clk = {
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+ .name = "usart1_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_US1,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk usart2_clk = {
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+ .name = "usart2_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_US2,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk usart3_clk = {
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+ .name = "usart3_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_US3,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk spi_clk = {
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+ .name = "spi_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_SPI,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk pioA_clk = {
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+ .name = "pioA_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_PIOA,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk pioB_clk = {
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+ .name = "pioB_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_PIOB,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk pioC_clk = {
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+ .name = "pioC_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_PIOC,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk pioD_clk = {
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+ .name = "pioD_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_PIOD,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk ssc0_clk = {
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+ .name = "ssc0_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_SSC0,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk ssc1_clk = {
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+ .name = "ssc1_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_SSC1,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk ssc2_clk = {
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+ .name = "ssc2_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_SSC2,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc0_clk = {
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+ .name = "tc0_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC0,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc1_clk = {
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+ .name = "tc1_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC1,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc2_clk = {
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+ .name = "tc2_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC2,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc3_clk = {
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+ .name = "tc3_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC3,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc4_clk = {
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+ .name = "tc4_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC4,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+static struct clk tc5_clk = {
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+ .name = "tc5_clk",
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+ .pmc_mask = 1 << AT91RM9200_ID_TC5,
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+ .type = CLK_TYPE_PERIPHERAL,
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+};
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+
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+static struct clk *periph_clocks[] __initdata = {
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+ &pioA_clk,
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+ &pioB_clk,
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+ &pioC_clk,
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+ &pioD_clk,
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+ &usart0_clk,
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+ &usart1_clk,
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+ &usart2_clk,
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+ &usart3_clk,
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+ &mmc_clk,
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+ &udc_clk,
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+ &twi_clk,
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+ &spi_clk,
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+ &ssc0_clk,
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+ &ssc1_clk,
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+ &ssc2_clk,
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+ &tc0_clk,
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+ &tc1_clk,
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+ &tc2_clk,
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+ &tc3_clk,
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+ &tc4_clk,
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+ &tc5_clk,
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+ &ohci_clk,
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+ ðer_clk,
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+ // irq0 .. irq6
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+};
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+
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+static struct clk_lookup periph_clocks_lookups[] = {
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+ CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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+ CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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+ CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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+ CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
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+ CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
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+ CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
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