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@@ -718,3 +718,87 @@
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/*
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* Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
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* PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
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+ * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
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+ */
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+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
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+#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
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+
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+/* Used by PRM_MODEM_IF_CTRL */
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+#define OMAP4430_MODEM_READY_SHIFT 1
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+#define OMAP4430_MODEM_READY_MASK (1 << 1)
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+
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+/* Used by PRM_MODEM_IF_CTRL */
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+#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
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+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
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+
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+/* Used by PRM_MODEM_IF_CTRL */
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+#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
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+#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
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+
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+/* Used by PRM_MODEM_IF_CTRL */
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+#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
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+#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
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+#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
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+#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
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+
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+/* Used by PM_MPU_PWRSTST */
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+#define OMAP4430_MPU_L1_STATEST_SHIFT 4
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+#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
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+#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
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+#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
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+
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+/* Used by PM_MPU_PWRSTST */
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+#define OMAP4430_MPU_L2_STATEST_SHIFT 6
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+#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
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+#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
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+
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+/* Used by PM_MPU_PWRSTCTRL */
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+#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
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+#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
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+
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+/* Used by PM_MPU_PWRSTST */
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+#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
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+#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
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+
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+/* Used by PRM_RSTST */
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+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
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+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
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+
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+/* Used by PRM_RSTST */
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+#define OMAP4430_MPU_WDT_RST_SHIFT 3
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+#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
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+
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+/* Used by PM_L4PER_PWRSTCTRL */
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+#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
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+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
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+
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+/* Used by PM_L4PER_PWRSTCTRL */
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+#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
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+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
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+
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+/* Used by PM_L4PER_PWRSTST */
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+#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
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+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
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+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
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+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
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