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@@ -928,3 +928,81 @@ void __init_or_cpufreq s3c64xx_setup_clocks(void)
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printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
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hclk2, hclk, pclk);
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+
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+ clk_fout_mpll.rate = mpll;
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+ clk_fout_epll.rate = epll;
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+ clk_fout_apll.rate = apll;
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+
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+ clk_h2.rate = hclk2;
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+ clk_h.rate = hclk;
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+ clk_p.rate = pclk;
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+ clk_f.rate = fclk;
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+
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+ for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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+ s3c_set_clksrc(init_parents[ptr], true);
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+
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+ for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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+ s3c_set_clksrc(&clksrcs[ptr], true);
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+}
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+
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+static struct clk *clks1[] __initdata = {
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+ &clk_ext_xtal_mux,
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+ &clk_iis_cd0,
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+ &clk_iis_cd1,
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+ &clk_iisv4_cd,
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+ &clk_pcm_cd,
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+ &clk_mout_epll.clk,
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+ &clk_mout_mpll.clk,
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+ &clk_dout_mpll,
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+ &clk_arm,
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+};
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+
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+static struct clk *clks[] __initdata = {
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+ &clk_ext,
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+ &clk_epll,
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+ &clk_27m,
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+ &clk_48m,
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+ &clk_h2,
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+ &clk_xusbxti,
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+};
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+
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+/**
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+ * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
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+ * @xtal: The rate for the clock crystal feeding the PLLs.
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+ * @armclk_divlimit: Divisor mask for ARMCLK.
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+ *
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+ * Register the clocks for the S3C6400 and S3C6410 SoC range, such
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+ * as ARMCLK as well as the necessary parent clocks.
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+ *
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+ * This call does not setup the clocks, which is left to the
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+ * s3c64xx_setup_clocks() call which may be needed by the cpufreq
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+ * or resume code to re-set the clocks if the bootloader has changed
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+ * them.
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+ */
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+void __init s3c64xx_register_clocks(unsigned long xtal,
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+ unsigned armclk_divlimit)
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+{
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+ unsigned int cnt;
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+
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+ armclk_mask = armclk_divlimit;
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+
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+ s3c24xx_register_baseclocks(xtal);
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+ s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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+
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+ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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+
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+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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+
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+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
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+ for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
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+ s3c_disable_clocks(clk_cdev[cnt], 1);
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+
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+ s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
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+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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+ for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
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+ s3c_register_clksrc(clksrc_cdev[cnt], 1);
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+ clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
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+
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+ s3c_pwmclk_init();
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+}
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沈瑞清