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@@ -323,3 +323,79 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
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*
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* ioremap takes a PCI memory address, as specified in
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* Documentation/io-mapping.txt.
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+ *
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+ */
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+#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
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+#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
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+#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
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+#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
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+#define iounmap __arm_iounmap
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+
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+/*
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+ * io{read,write}{8,16,32} macros
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+ */
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+#ifndef ioread8
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+#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
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+#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
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+#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
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+
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+#define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
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+#define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
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+
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+#define iowrite8(v,p) ({ __iowmb(); __raw_writeb(v, p); })
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+#define iowrite16(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
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+#define iowrite32(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
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+
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+#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
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+#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
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+
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+#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
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+#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
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+#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
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+
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+#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
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+#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
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+#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
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+
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+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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+extern void ioport_unmap(void __iomem *addr);
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+#endif
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+
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+struct pci_dev;
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+
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+extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
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+
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+/*
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+ * can the hardware map this into one segment or not, given no other
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+ * constraints.
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+ */
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+#define BIOVEC_MERGEABLE(vec1, vec2) \
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+ ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
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+
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+#ifdef CONFIG_MMU
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+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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+extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
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+extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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+extern int devmem_is_allowed(unsigned long pfn);
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+#endif
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+
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+/*
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+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
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+ * access
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+ */
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+#define xlate_dev_mem_ptr(p) __va(p)
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+
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+/*
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+ * Convert a virtual cached pointer to an uncached pointer
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+ */
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+#define xlate_dev_kmem_ptr(p) p
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+
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+/*
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+ * Register ISA memory and port locations for glibc iopl/inb/outb
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+ * emulation.
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+ */
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+extern void register_isa_ports(unsigned int mmio, unsigned int io,
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+ unsigned int io_shift);
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+
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+#endif /* __KERNEL__ */
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+#endif /* __ASM_ARM_IO_H */
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李欣儒