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@@ -544,3 +544,139 @@
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#define nCLEAR_DATATOGGLE_T 0x0
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#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
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#define nINCOMPTX_T 0x0
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+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
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+#define nDMAREQMODE_T 0x0
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+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
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+#define nFORCE_DATATOGGLE_T 0x0
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+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
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+#define nDMAREQ_ENA_T 0x0
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+#define ISO_T 0x4000 /* enable Isochronous transfers */
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+#define nISO_T 0x0
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+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
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+#define nAUTOSET_T 0x0
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+#define ERROR_TH 0x4 /* error condition host mode */
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+#define nERROR_TH 0x0
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+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
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+#define nSTALL_RECEIVED_TH 0x0
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+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
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+#define nNAK_TIMEOUT_TH 0x0
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+
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+/* Bit masks for USB_TXCOUNT */
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+
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+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
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+
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+/* Bit masks for USB_RXCSR */
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+
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+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
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+#define nRXPKTRDY_R 0x0
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+#define FIFO_FULL_R 0x2 /* FIFO not empty */
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+#define nFIFO_FULL_R 0x0
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+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
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+#define nOVERRUN_R 0x0
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+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
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+#define nDATAERROR_R 0x0
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+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
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+#define nFLUSHFIFO_R 0x0
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+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
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+#define nSTALL_SEND_R 0x0
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+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
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+#define nSTALL_SENT_R 0x0
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+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
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+#define nCLEAR_DATATOGGLE_R 0x0
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+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
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+#define nINCOMPRX_R 0x0
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+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
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+#define nDMAREQMODE_R 0x0
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+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
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+#define nDISNYET_R 0x0
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+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
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+#define nDMAREQ_ENA_R 0x0
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+#define ISO_R 0x4000 /* enable Isochronous transfers */
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+#define nISO_R 0x0
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+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
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+#define nAUTOCLEAR_R 0x0
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+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
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+#define nERROR_RH 0x0
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+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
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+#define nREQPKT_RH 0x0
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+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
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+#define nSTALL_RECEIVED_RH 0x0
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+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
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+#define nINCOMPRX_RH 0x0
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+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
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+#define nDMAREQMODE_RH 0x0
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+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
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+#define nAUTOREQ_RH 0x0
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+
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+/* Bit masks for USB_RXCOUNT */
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+
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+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
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+
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+/* Bit masks for USB_TXTYPE */
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+
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+#define TARGET_EP_NO_T 0xf /* EP number */
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+#define PROTOCOL_T 0xc /* transfer type */
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+
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+/* Bit masks for USB_TXINTERVAL */
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+
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+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
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+
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+/* Bit masks for USB_RXTYPE */
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+
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+#define TARGET_EP_NO_R 0xf /* EP number */
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+#define PROTOCOL_R 0xc /* transfer type */
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+
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+/* Bit masks for USB_RXINTERVAL */
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+
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+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
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+
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+/* Bit masks for USB_DMA_INTERRUPT */
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+
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+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
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+#define nDMA0_INT 0x0
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+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
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+#define nDMA1_INT 0x0
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+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
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+#define nDMA2_INT 0x0
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+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
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+#define nDMA3_INT 0x0
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+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
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+#define nDMA4_INT 0x0
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+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
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+#define nDMA5_INT 0x0
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+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
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+#define nDMA6_INT 0x0
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+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
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+#define nDMA7_INT 0x0
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+
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+/* Bit masks for USB_DMAxCONTROL */
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+
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+#define DMA_ENA 0x1 /* DMA enable */
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+#define nDMA_ENA 0x0
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+#define DIRECTION 0x2 /* direction of DMA transfer */
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+#define nDIRECTION 0x0
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+#define MODE 0x4 /* DMA Bus error */
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+#define nMODE 0x0
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+#define INT_ENA 0x8 /* Interrupt enable */
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+#define nINT_ENA 0x0
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+#define EPNUM 0xf0 /* EP number */
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+#define BUSERROR 0x100 /* DMA Bus error */
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+#define nBUSERROR 0x0
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+
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+/* Bit masks for USB_DMAxADDRHIGH */
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+
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+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
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+
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+/* Bit masks for USB_DMAxADDRLOW */
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+
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+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
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+
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+/* Bit masks for USB_DMAxCOUNTHIGH */
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+
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+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
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+
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+/* Bit masks for USB_DMAxCOUNTLOW */
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+
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+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
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+
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+#endif /* _DEF_BF525_H */
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韩正义