|
@@ -2326,3 +2326,172 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
|
|
|
#if defined(CONFIG_SND_SOC_ADAU1361) || defined(CONFIG_SND_SOC_ADAU1361_MODULE)
|
|
|
{
|
|
|
I2C_BOARD_INFO("adau1361", 0x38),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_SND_SOC_ADAU1701) || defined(CONFIG_SND_SOC_ADAU1701_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("adau1701", 0x34),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("ad5258", 0x18),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("ssm2602", 0x1b),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("ad5398", 0xC),
|
|
|
+ .platform_data = (void *)&ad5398_regulator_data,
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("adp8860", 0x2A),
|
|
|
+ .platform_data = (void *)&adp8860_pdata,
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("adau1373", 0x1A),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
|
|
|
+ {
|
|
|
+ I2C_BOARD_INFO("ad5252", 0x2e),
|
|
|
+ },
|
|
|
+#endif
|
|
|
+};
|
|
|
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
|
|
|
+|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
|
|
|
+unsigned short bfin_sport0_peripherals[] = {
|
|
|
+ P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
|
|
|
+ P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
|
|
|
+};
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
|
|
+#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
|
|
+static struct resource bfin_sport0_uart_resources[] = {
|
|
|
+ {
|
|
|
+ .start = SPORT0_TCR1,
|
|
|
+ .end = SPORT0_MRCS3+4,
|
|
|
+ .flags = IORESOURCE_MEM,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT0_RX,
|
|
|
+ .end = IRQ_SPORT0_RX+1,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT0_ERROR,
|
|
|
+ .end = IRQ_SPORT0_ERROR,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct platform_device bfin_sport0_uart_device = {
|
|
|
+ .name = "bfin-sport-uart",
|
|
|
+ .id = 0,
|
|
|
+ .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
|
|
|
+ .resource = bfin_sport0_uart_resources,
|
|
|
+ .dev = {
|
|
|
+ .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
|
|
+ },
|
|
|
+};
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
|
|
+static struct resource bfin_sport1_uart_resources[] = {
|
|
|
+ {
|
|
|
+ .start = SPORT1_TCR1,
|
|
|
+ .end = SPORT1_MRCS3+4,
|
|
|
+ .flags = IORESOURCE_MEM,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT1_RX,
|
|
|
+ .end = IRQ_SPORT1_RX+1,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT1_ERROR,
|
|
|
+ .end = IRQ_SPORT1_ERROR,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static unsigned short bfin_sport1_peripherals[] = {
|
|
|
+ P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
|
|
|
+ P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
|
|
|
+};
|
|
|
+
|
|
|
+static struct platform_device bfin_sport1_uart_device = {
|
|
|
+ .name = "bfin-sport-uart",
|
|
|
+ .id = 1,
|
|
|
+ .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
|
|
|
+ .resource = bfin_sport1_uart_resources,
|
|
|
+ .dev = {
|
|
|
+ .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
|
|
+ },
|
|
|
+};
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
|
|
|
+static struct resource bfin_sport0_resources[] = {
|
|
|
+ {
|
|
|
+ .start = SPORT0_TCR1,
|
|
|
+ .end = SPORT0_MRCS3+4,
|
|
|
+ .flags = IORESOURCE_MEM,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT0_RX,
|
|
|
+ .end = IRQ_SPORT0_RX+1,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT0_TX,
|
|
|
+ .end = IRQ_SPORT0_TX+1,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = IRQ_SPORT0_ERROR,
|
|
|
+ .end = IRQ_SPORT0_ERROR,
|
|
|
+ .flags = IORESOURCE_IRQ,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = CH_SPORT0_TX,
|
|
|
+ .end = CH_SPORT0_TX,
|
|
|
+ .flags = IORESOURCE_DMA,
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .start = CH_SPORT0_RX,
|
|
|
+ .end = CH_SPORT0_RX,
|
|
|
+ .flags = IORESOURCE_DMA,
|
|
|
+ },
|
|
|
+};
|
|
|
+static struct platform_device bfin_sport0_device = {
|
|
|
+ .name = "bfin_sport_raw",
|
|
|
+ .id = 0,
|
|
|
+ .num_resources = ARRAY_SIZE(bfin_sport0_resources),
|
|
|
+ .resource = bfin_sport0_resources,
|
|
|
+ .dev = {
|
|
|
+ .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
|
|
+ },
|
|
|
+};
|
|
|
+#endif
|
|
|
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
|
|
|
+#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
|
|
|
+/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
|
|
|
+
|
|
|
+#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
|
|
|
+#define PATA_INT IRQ_PF5
|
|
|
+static struct pata_platform_info bfin_pata_platform_data = {
|
|
|
+ .ioport_shift = 1,
|
|
|
+ .irq_flags = IRQF_TRIGGER_HIGH,
|
|
|
+};
|
|
|
+
|
|
|
+static struct resource bfin_pata_resources[] = {
|
|
|
+ {
|
|
|
+ .start = 0x20314020,
|