|
|
@@ -145,3 +145,189 @@ typedef struct quicc {
|
|
|
volatile unsigned long memc_or7; /* option register 3 */
|
|
|
volatile unsigned char RESERVED9[0x28]; /* Reserved area */
|
|
|
/* TEST */
|
|
|
+ volatile unsigned short test_tstmra; /* master shift a */
|
|
|
+ volatile unsigned short test_tstmrb; /* master shift b */
|
|
|
+ volatile unsigned short test_tstsc; /* shift count */
|
|
|
+ volatile unsigned short test_tstrc; /* repetition counter */
|
|
|
+ volatile unsigned short test_creg; /* control */
|
|
|
+ volatile unsigned short test_dreg; /* destributed register */
|
|
|
+ volatile unsigned char RESERVED58[0x404]; /* Reserved area */
|
|
|
+ /* IDMA1 */
|
|
|
+ volatile unsigned short idma_iccr; /* channel configuration reg*/
|
|
|
+ volatile unsigned char RESERVED19[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short idma1_cmr; /* dma mode reg */
|
|
|
+ volatile unsigned char RESERVED68[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned long idma1_sapr; /* dma source addr ptr */
|
|
|
+ volatile unsigned long idma1_dapr; /* dma destination addr ptr */
|
|
|
+ volatile unsigned long idma1_bcr; /* dma byte count reg */
|
|
|
+ volatile unsigned char idma1_fcr; /* function code reg */
|
|
|
+ volatile unsigned char RESERVED20; /* Reserved area */
|
|
|
+ volatile unsigned char idma1_cmar; /* channel mask reg */
|
|
|
+ volatile unsigned char RESERVED21; /* Reserved area */
|
|
|
+ volatile unsigned char idma1_csr; /* channel status reg */
|
|
|
+ volatile unsigned char RESERVED22[0x3]; /* Reserved area */
|
|
|
+ /* SDMA */
|
|
|
+ volatile unsigned char sdma_sdsr; /* status reg */
|
|
|
+ volatile unsigned char RESERVED23; /* Reserved area */
|
|
|
+ volatile unsigned short sdma_sdcr; /* configuration reg */
|
|
|
+ volatile unsigned long sdma_sdar; /* address reg */
|
|
|
+ /* IDMA2 */
|
|
|
+ volatile unsigned char RESERVED69[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short idma2_cmr; /* dma mode reg */
|
|
|
+ volatile unsigned long idma2_sapr; /* dma source addr ptr */
|
|
|
+ volatile unsigned long idma2_dapr; /* dma destination addr ptr */
|
|
|
+ volatile unsigned long idma2_bcr; /* dma byte count reg */
|
|
|
+ volatile unsigned char idma2_fcr; /* function code reg */
|
|
|
+ volatile unsigned char RESERVED24; /* Reserved area */
|
|
|
+ volatile unsigned char idma2_cmar; /* channel mask reg */
|
|
|
+ volatile unsigned char RESERVED25; /* Reserved area */
|
|
|
+ volatile unsigned char idma2_csr; /* channel status reg */
|
|
|
+ volatile unsigned char RESERVED26[0x7]; /* Reserved area */
|
|
|
+ /* Interrupt Controller */
|
|
|
+ volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
|
|
|
+ volatile unsigned long intr_cipr; /* CP interrupt pending reg */
|
|
|
+ volatile unsigned long intr_cimr; /* CP interrupt mask reg */
|
|
|
+ volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
|
|
|
+ /* Parallel I/O */
|
|
|
+ volatile unsigned short pio_padir; /* port A data direction reg */
|
|
|
+ volatile unsigned short pio_papar; /* port A pin assignment reg */
|
|
|
+ volatile unsigned short pio_paodr; /* port A open drain reg */
|
|
|
+ volatile unsigned short pio_padat; /* port A data register */
|
|
|
+ volatile unsigned char RESERVED28[0x8]; /* Reserved area */
|
|
|
+ volatile unsigned short pio_pcdir; /* port C data direction reg*/
|
|
|
+ volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
|
|
|
+ volatile unsigned short pio_pcso; /* port C special options */
|
|
|
+ volatile unsigned short pio_pcdat; /* port C data register */
|
|
|
+ volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
|
|
|
+ volatile unsigned char RESERVED29[0x16]; /* Reserved area */
|
|
|
+ /* Timer */
|
|
|
+ volatile unsigned short timer_tgcr; /* timer global configuration reg */
|
|
|
+ volatile unsigned char RESERVED30[0xe]; /* Reserved area */
|
|
|
+ volatile unsigned short timer_tmr1; /* timer 1 mode reg */
|
|
|
+ volatile unsigned short timer_tmr2; /* timer 2 mode reg */
|
|
|
+ volatile unsigned short timer_trr1; /* timer 1 referance reg */
|
|
|
+ volatile unsigned short timer_trr2; /* timer 2 referance reg */
|
|
|
+ volatile unsigned short timer_tcr1; /* timer 1 capture reg */
|
|
|
+ volatile unsigned short timer_tcr2; /* timer 2 capture reg */
|
|
|
+ volatile unsigned short timer_tcn1; /* timer 1 counter reg */
|
|
|
+ volatile unsigned short timer_tcn2; /* timer 2 counter reg */
|
|
|
+ volatile unsigned short timer_tmr3; /* timer 3 mode reg */
|
|
|
+ volatile unsigned short timer_tmr4; /* timer 4 mode reg */
|
|
|
+ volatile unsigned short timer_trr3; /* timer 3 referance reg */
|
|
|
+ volatile unsigned short timer_trr4; /* timer 4 referance reg */
|
|
|
+ volatile unsigned short timer_tcr3; /* timer 3 capture reg */
|
|
|
+ volatile unsigned short timer_tcr4; /* timer 4 capture reg */
|
|
|
+ volatile unsigned short timer_tcn3; /* timer 3 counter reg */
|
|
|
+ volatile unsigned short timer_tcn4; /* timer 4 counter reg */
|
|
|
+ volatile unsigned short timer_ter1; /* timer 1 event reg */
|
|
|
+ volatile unsigned short timer_ter2; /* timer 2 event reg */
|
|
|
+ volatile unsigned short timer_ter3; /* timer 3 event reg */
|
|
|
+ volatile unsigned short timer_ter4; /* timer 4 event reg */
|
|
|
+ volatile unsigned char RESERVED34[0x8]; /* Reserved area */
|
|
|
+ /* CP */
|
|
|
+ volatile unsigned short cp_cr; /* command register */
|
|
|
+ volatile unsigned char RESERVED35[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short cp_rccr; /* main configuration reg */
|
|
|
+ volatile unsigned char RESERVED37; /* Reserved area */
|
|
|
+ volatile unsigned char cp_rmds; /* development support status reg */
|
|
|
+ volatile unsigned long cp_rmdr; /* development support control reg */
|
|
|
+ volatile unsigned short cp_rctr1; /* ram break register 1 */
|
|
|
+ volatile unsigned short cp_rctr2; /* ram break register 2 */
|
|
|
+ volatile unsigned short cp_rctr3; /* ram break register 3 */
|
|
|
+ volatile unsigned short cp_rctr4; /* ram break register 4 */
|
|
|
+ volatile unsigned char RESERVED59[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short cp_rter; /* RISC timers event reg */
|
|
|
+ volatile unsigned char RESERVED38[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short cp_rtmr; /* RISC timers mask reg */
|
|
|
+ volatile unsigned char RESERVED39[0x14]; /* Reserved area */
|
|
|
+ /* BRG */
|
|
|
+ union {
|
|
|
+ volatile unsigned long l;
|
|
|
+ struct {
|
|
|
+ volatile unsigned short BRGC_RESERV:14;
|
|
|
+ volatile unsigned short rst:1;
|
|
|
+ volatile unsigned short en:1;
|
|
|
+ volatile unsigned short extc:2;
|
|
|
+ volatile unsigned short atb:1;
|
|
|
+ volatile unsigned short cd:12;
|
|
|
+ volatile unsigned short div16:1;
|
|
|
+ } b;
|
|
|
+ } brgc[4]; /* BRG1-BRG4 configuration regs*/
|
|
|
+ /* SCC registers */
|
|
|
+ struct scc_regs {
|
|
|
+ union {
|
|
|
+ struct {
|
|
|
+ /* Low word. */
|
|
|
+ volatile unsigned short GSMR_RESERV2:1;
|
|
|
+ volatile unsigned short edge:2;
|
|
|
+ volatile unsigned short tci:1;
|
|
|
+ volatile unsigned short tsnc:2;
|
|
|
+ volatile unsigned short rinv:1;
|
|
|
+ volatile unsigned short tinv:1;
|
|
|
+ volatile unsigned short tpl:3;
|
|
|
+ volatile unsigned short tpp:2;
|
|
|
+ volatile unsigned short tend:1;
|
|
|
+ volatile unsigned short tdcr:2;
|
|
|
+ volatile unsigned short rdcr:2;
|
|
|
+ volatile unsigned short renc:3;
|
|
|
+ volatile unsigned short tenc:3;
|
|
|
+ volatile unsigned short diag:2;
|
|
|
+ volatile unsigned short enr:1;
|
|
|
+ volatile unsigned short ent:1;
|
|
|
+ volatile unsigned short mode:4;
|
|
|
+ /* High word. */
|
|
|
+ volatile unsigned short GSMR_RESERV1:14;
|
|
|
+ volatile unsigned short pri:1;
|
|
|
+ volatile unsigned short gde:1;
|
|
|
+ volatile unsigned short tcrc:2;
|
|
|
+ volatile unsigned short revd:1;
|
|
|
+ volatile unsigned short trx:1;
|
|
|
+ volatile unsigned short ttx:1;
|
|
|
+ volatile unsigned short cdp:1;
|
|
|
+ volatile unsigned short ctsp:1;
|
|
|
+ volatile unsigned short cds:1;
|
|
|
+ volatile unsigned short ctss:1;
|
|
|
+ volatile unsigned short tfl:1;
|
|
|
+ volatile unsigned short rfw:1;
|
|
|
+ volatile unsigned short txsy:1;
|
|
|
+ volatile unsigned short synl:2;
|
|
|
+ volatile unsigned short rtsm:1;
|
|
|
+ volatile unsigned short rsyn:1;
|
|
|
+ } b;
|
|
|
+ struct {
|
|
|
+ volatile unsigned long low;
|
|
|
+ volatile unsigned long high;
|
|
|
+ } w;
|
|
|
+ } scc_gsmr; /* SCC general mode reg */
|
|
|
+ volatile unsigned short scc_psmr; /* protocol specific mode reg */
|
|
|
+ volatile unsigned char RESERVED42[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short scc_todr; /* SCC transmit on demand */
|
|
|
+ volatile unsigned short scc_dsr; /* SCC data sync reg */
|
|
|
+ volatile unsigned short scc_scce; /* SCC event reg */
|
|
|
+ volatile unsigned char RESERVED43[0x2];/* Reserved area */
|
|
|
+ volatile unsigned short scc_sccm; /* SCC mask reg */
|
|
|
+ volatile unsigned char RESERVED44[0x1];/* Reserved area */
|
|
|
+ volatile unsigned char scc_sccs; /* SCC status reg */
|
|
|
+ volatile unsigned char RESERVED45[0x8]; /* Reserved area */
|
|
|
+ } scc_regs[4];
|
|
|
+ /* SMC */
|
|
|
+ struct smc_regs {
|
|
|
+ volatile unsigned char RESERVED46[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned short smc_smcmr; /* SMC mode reg */
|
|
|
+ volatile unsigned char RESERVED60[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned char smc_smce; /* SMC event reg */
|
|
|
+ volatile unsigned char RESERVED47[0x3]; /* Reserved area */
|
|
|
+ volatile unsigned char smc_smcm; /* SMC mask reg */
|
|
|
+ volatile unsigned char RESERVED48[0x5]; /* Reserved area */
|
|
|
+ } smc_regs[2];
|
|
|
+ /* SPI */
|
|
|
+ volatile unsigned short spi_spmode; /* SPI mode reg */
|
|
|
+ volatile unsigned char RESERVED51[0x4]; /* Reserved area */
|
|
|
+ volatile unsigned char spi_spie; /* SPI event reg */
|
|
|
+ volatile unsigned char RESERVED52[0x3]; /* Reserved area */
|
|
|
+ volatile unsigned char spi_spim; /* SPI mask reg */
|
|
|
+ volatile unsigned char RESERVED53[0x2]; /* Reserved area */
|
|
|
+ volatile unsigned char spi_spcom; /* SPI command reg */
|
|
|
+ volatile unsigned char RESERVED54[0x4]; /* Reserved area */
|
|
|
+ /* PIP */
|
|
|
+ volatile unsigned short pip_pipc; /* pip configuration reg */
|
张婷