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@@ -247,3 +247,92 @@
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#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
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#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
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#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
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+#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
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+#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
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+#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
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+#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
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+#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
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+#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
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+#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
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+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
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+#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
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+#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
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+#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
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+#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
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+
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+
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+
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+
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+/* Two Wire Interface Registers (TWI0) */
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+
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+/* SPORT1 Registers */
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+
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+
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+/* SMC Registers */
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+#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
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+#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
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+#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
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+#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
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+#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
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+#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
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+#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
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+#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
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+#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
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+#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
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+#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
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+#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
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+#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
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+#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
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+#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
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+#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
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+#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
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+#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
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+#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
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+#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
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+#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
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+#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
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+#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
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+#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
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+#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
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+#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
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+#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
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+
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+/* DDR2 Memory Control Registers */
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+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
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+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
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+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
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+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
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+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
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+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
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+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
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+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
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+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
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+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
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+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
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+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
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+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
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+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
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+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
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+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
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+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
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+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
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+
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+/* DDR BankRead and Write Count Registers */
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+
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+
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+/* DMA Channel 0 Registers */
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+
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+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
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+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
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+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
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+#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
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+#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
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+#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
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+#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
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+#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
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+#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
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+#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
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+#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
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+#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
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+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
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