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@@ -593,3 +593,78 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
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.dmaor_init = DMAOR_DME,
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};
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+static struct resource sh73a0_dmae_resources[] = {
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+ {
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+ /* Registers including DMAOR and channels including DMARSx */
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+ .start = 0xfe000020,
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+ .end = 0xfe008a00 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "error_irq",
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+ .start = gic_spi(129),
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+ .end = gic_spi(129),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ /* IRQ for channels 0-19 */
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+ .start = gic_spi(109),
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+ .end = gic_spi(128),
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device dma0_device = {
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+ .name = "sh-dma-engine",
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+ .id = 0,
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+ .resource = sh73a0_dmae_resources,
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+ .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
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+ .dev = {
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+ .platform_data = &sh73a0_dmae_platform_data,
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+ },
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+};
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+
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+/* MPDMAC */
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+static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
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+ {
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+ .slave_id = SHDMA_SLAVE_FSI2A_RX,
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+ .addr = 0xec230020,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xd6, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2A_TX,
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+ .addr = 0xec230024,
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+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xd5, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2C_RX,
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+ .addr = 0xec230060,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xda, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2C_TX,
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+ .addr = 0xec230064,
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+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
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+ .mid_rid = 0xd9, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2B_RX,
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+ .addr = 0xec240020,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0x8e, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2B_TX,
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+ .addr = 0xec240024,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0x8d, /* CHECK ME */
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+ }, {
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+ .slave_id = SHDMA_SLAVE_FSI2D_RX,
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+ .addr = 0xec240060,
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+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
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+ .mid_rid = 0x9a, /* CHECK ME */
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+ },
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+};
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+
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+#define MPDMA_CHANNEL(a, b, c) \
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+{ \
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+ .offset = a, \
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+ .dmars = b, \
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