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+/*
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+ * MT regs definitions, follows on from mipsregs.h
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+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
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+ * Elizabeth Clarke et. al.
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+ *
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+ */
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+#ifndef _ASM_MIPSMTREGS_H
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+#define _ASM_MIPSMTREGS_H
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+
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+#include <asm/mipsregs.h>
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+#include <asm/war.h>
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+
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+#ifndef __ASSEMBLY__
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+
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+/*
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+ * C macros
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+ */
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+
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+#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
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+#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
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+
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+#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
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+#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
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+
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+#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
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+#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
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+
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+#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
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+#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
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+
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+#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
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+#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
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+
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+#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
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+#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
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+
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+#define read_c0_tcbind() __read_32bit_c0_register($2, 2)
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+
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+#define read_c0_tccontext() __read_32bit_c0_register($2, 5)
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+#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
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+
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+#else /* Assembly */
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+/*
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+ * Macros for use in assembly language code
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+ */
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+
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+#define CP0_MVPCONTROL $0, 1
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+#define CP0_MVPCONF0 $0, 2
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+#define CP0_MVPCONF1 $0, 3
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+#define CP0_VPECONTROL $1, 1
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+#define CP0_VPECONF0 $1, 2
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+#define CP0_VPECONF1 $1, 3
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+#define CP0_YQMASK $1, 4
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+#define CP0_VPESCHEDULE $1, 5
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+#define CP0_VPESCHEFBK $1, 6
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+#define CP0_TCSTATUS $2, 1
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+#define CP0_TCBIND $2, 2
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+#define CP0_TCRESTART $2, 3
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+#define CP0_TCHALT $2, 4
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+#define CP0_TCCONTEXT $2, 5
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+#define CP0_TCSCHEDULE $2, 6
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+#define CP0_TCSCHEFBK $2, 7
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+#define CP0_SRSCONF0 $6, 1
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+#define CP0_SRSCONF1 $6, 2
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+#define CP0_SRSCONF2 $6, 3
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+#define CP0_SRSCONF3 $6, 4
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+#define CP0_SRSCONF4 $6, 5
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+
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+#endif
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+
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+/* MVPControl fields */
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+#define MVPCONTROL_EVP (_ULCAST_(1))
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+
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+#define MVPCONTROL_VPC_SHIFT 1
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+#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
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+
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+#define MVPCONTROL_STLB_SHIFT 2
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+#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
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+
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+
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+/* MVPConf0 fields */
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+#define MVPCONF0_PTC_SHIFT 0
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+#define MVPCONF0_PTC ( _ULCAST_(0xff))
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+#define MVPCONF0_PVPE_SHIFT 10
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+#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
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+#define MVPCONF0_TCA_SHIFT 15
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+#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
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