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+/*
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+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
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+ * Written by Hennus Bergman, 1992.
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+ * High DMA channel support & info by Hannu Savolainen
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+ * and John Boyd, Nov. 1992.
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+ *
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+ * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
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+ * and can only be used for expansion cards. Onboard DMA controllers, such
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+ * as the R4030 on Jazz boards behave totally different!
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+ */
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+
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+#ifndef _ASM_DMA_H
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+#define _ASM_DMA_H
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+
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+#include <asm/io.h> /* need byte IO */
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+#include <linux/spinlock.h> /* And spinlocks */
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+#include <linux/delay.h>
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+
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+
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+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
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+#define dma_outb outb_p
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+#else
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+#define dma_outb outb
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+#endif
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+
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+#define dma_inb inb
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+
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+/*
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+ * NOTES about DMA transfers:
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+ *
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+ * controller 1: channels 0-3, byte operations, ports 00-1F
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+ * controller 2: channels 4-7, word operations, ports C0-DF
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+ *
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+ * - ALL registers are 8 bits only, regardless of transfer size
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+ * - channel 4 is not used - cascades 1 into 2.
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+ * - channels 0-3 are byte - addresses/counts are for physical bytes
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+ * - channels 5-7 are word - addresses/counts are for physical words
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+ * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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+ * - transfer count loaded to registers is 1 less than actual count
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+ * - controller 2 offsets are all even (2x offsets for controller 1)
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+ * - page registers for 5-7 don't use data bit 0, represent 128K pages
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+ * - page registers for 0-3 use bit 0, represent 64K pages
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+ *
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+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
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+ * Note that addresses loaded into registers must be _physical_ addresses,
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+ * not logical addresses (which may differ if paging is active).
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+ *
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+ * Address mapping for channels 0-3:
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+ *
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+ * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
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+ * | ... | | ... | | ... |
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+ * | ... | | ... | | ... |
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+ * | ... | | ... | | ... |
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+ * P7 ... P0 A7 ... A0 A7 ... A0
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+ * | Page | Addr MSB | Addr LSB | (DMA registers)
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+ *
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+ * Address mapping for channels 5-7:
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+ *
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+ * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
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+ * | ... | \ \ ... \ \ \ ... \ \
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+ * | ... | \ \ ... \ \ \ ... \ (not used)
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+ * | ... | \ \ ... \ \ \ ... \
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+ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
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+ * | Page | Addr MSB | Addr LSB | (DMA registers)
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+ *
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+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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+ * the hardware level, so odd-byte transfers aren't possible).
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+ *
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+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
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+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
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+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
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+ *
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+ */
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+
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+#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
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+#define MAX_DMA_CHANNELS 8
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+#endif
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+
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+/*
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+ * The maximum address in KSEG0 that we can perform a DMA transfer to on this
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+ * platform. This describes only the PC style part of the DMA logic like on
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+ * Deskstations or Acer PICA but not the much more versatile DMA logic used
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+ * for the local devices on Acer PICA or Magnums.
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+ */
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+#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
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+/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
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+#define MAX_DMA_ADDRESS PAGE_OFFSET
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+#else
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+#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
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+#endif
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+#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
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+
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+#ifndef MAX_DMA32_PFN
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+#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
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+#endif
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+
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+/* 8237 DMA controllers */
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+#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
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+#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
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+
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+/* DMA controller registers */
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+#define DMA1_CMD_REG 0x08 /* command register (w) */
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+#define DMA1_STAT_REG 0x08 /* status register (r) */
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+#define DMA1_REQ_REG 0x09 /* request register (w) */
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