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@@ -579,3 +579,84 @@ cia_save_srm_settings(int is_pyxis)
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/* Save some important registers. */
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saved_config.err_mask = *(vip)CIA_IOC_ERR_MASK;
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+ saved_config.cia_ctrl = *(vip)CIA_IOC_CIA_CTRL;
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+ saved_config.hae_mem = *(vip)CIA_IOC_HAE_MEM;
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+ saved_config.hae_io = *(vip)CIA_IOC_HAE_IO;
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+ saved_config.pci_dac_offset = *(vip)CIA_IOC_PCI_W_DAC;
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+
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+ if (is_pyxis)
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+ saved_config.cia_cnfg = *(vip)CIA_IOC_CIA_CNFG;
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+ else
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+ saved_config.cia_cnfg = 0;
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+
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+ /* Save DMA windows configuration. */
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+ for (i = 0; i < 4; i++) {
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+ saved_config.window[i].w_base = *(vip)CIA_IOC_PCI_Wn_BASE(i);
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+ saved_config.window[i].w_mask = *(vip)CIA_IOC_PCI_Wn_MASK(i);
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+ saved_config.window[i].t_base = *(vip)CIA_IOC_PCI_Tn_BASE(i);
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+ }
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+ mb();
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+}
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+
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+void
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+cia_restore_srm_settings(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < 4; i++) {
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+ *(vip)CIA_IOC_PCI_Wn_BASE(i) = saved_config.window[i].w_base;
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+ *(vip)CIA_IOC_PCI_Wn_MASK(i) = saved_config.window[i].w_mask;
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+ *(vip)CIA_IOC_PCI_Tn_BASE(i) = saved_config.window[i].t_base;
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+ }
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+
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+ *(vip)CIA_IOC_HAE_MEM = saved_config.hae_mem;
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+ *(vip)CIA_IOC_HAE_IO = saved_config.hae_io;
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+ *(vip)CIA_IOC_PCI_W_DAC = saved_config.pci_dac_offset;
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+ *(vip)CIA_IOC_ERR_MASK = saved_config.err_mask;
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+ *(vip)CIA_IOC_CIA_CTRL = saved_config.cia_ctrl;
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+
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+ if (saved_config.cia_cnfg) /* Must be pyxis. */
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+ *(vip)CIA_IOC_CIA_CNFG = saved_config.cia_cnfg;
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+
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+ mb();
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+}
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+#else /* ALPHA_RESTORE_SRM_SETUP */
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+#define cia_save_srm_settings(p) do {} while (0)
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+#define cia_restore_srm_settings() do {} while (0)
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+#endif /* ALPHA_RESTORE_SRM_SETUP */
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+
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+
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+static void __init
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+do_init_arch(int is_pyxis)
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+{
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+ struct pci_controller *hose;
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+ int temp, cia_rev, tbia_window;
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+
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+ cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK;
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+ printk("pci: cia revision %d%s\n",
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+ cia_rev, is_pyxis ? " (pyxis)" : "");
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+
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+ if (alpha_using_srm)
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+ cia_save_srm_settings(is_pyxis);
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+
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+ /* Set up error reporting. */
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+ temp = *(vip)CIA_IOC_ERR_MASK;
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+ temp &= ~(CIA_ERR_CPU_PE | CIA_ERR_MEM_NEM | CIA_ERR_PA_PTE_INV
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+ | CIA_ERR_RCVD_MAS_ABT | CIA_ERR_RCVD_TAR_ABT);
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+ *(vip)CIA_IOC_ERR_MASK = temp;
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+
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+ /* Clear all currently pending errors. */
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+ temp = *(vip)CIA_IOC_CIA_ERR;
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+ *(vip)CIA_IOC_CIA_ERR = temp;
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+
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+ /* Turn on mchecks. */
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+ temp = *(vip)CIA_IOC_CIA_CTRL;
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+ temp |= CIA_CTRL_FILL_ERR_EN | CIA_CTRL_MCHK_ERR_EN;
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+ *(vip)CIA_IOC_CIA_CTRL = temp;
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+
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+ /* Clear the CFG register, which gets used for PCI config space
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+ accesses. That is the way we want to use it, and we do not
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+ want to depend on what ARC or SRM might have left behind. */
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+ *(vip)CIA_IOC_CFG = 0;
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+
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+ /* Zero the HAEs. */
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