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@@ -5660,3 +5660,123 @@ static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
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.flags = ADDR_TYPE_RT
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.flags = ADDR_TYPE_RT
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},
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},
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{ }
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{ }
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+};
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+
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+/* l4_abe -> slimbus1 (dma) */
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+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
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+ .master = &omap44xx_l4_abe_hwmod,
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+ .slave = &omap44xx_slimbus1_hwmod,
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+ .clk = "ocp_abe_iclk",
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+ .addr = omap44xx_slimbus1_dma_addrs,
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+ .user = OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
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+ {
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+ .pa_start = 0x48076000,
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+ .pa_end = 0x480763ff,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> slimbus2 */
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+static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
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+ .master = &omap44xx_l4_per_hwmod,
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+ .slave = &omap44xx_slimbus2_hwmod,
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+ .clk = "l4_div_ck",
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+ .addr = omap44xx_slimbus2_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
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+ {
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+ .pa_start = 0x4a0dd000,
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+ .pa_end = 0x4a0dd03f,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_cfg -> smartreflex_core */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_smartreflex_core_hwmod,
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+ .clk = "l4_div_ck",
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+ .addr = omap44xx_smartreflex_core_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
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+ {
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+ .pa_start = 0x4a0db000,
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+ .pa_end = 0x4a0db03f,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_cfg -> smartreflex_iva */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_smartreflex_iva_hwmod,
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+ .clk = "l4_div_ck",
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+ .addr = omap44xx_smartreflex_iva_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
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+ {
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+ .pa_start = 0x4a0d9000,
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+ .pa_end = 0x4a0d903f,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_cfg -> smartreflex_mpu */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_smartreflex_mpu_hwmod,
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+ .clk = "l4_div_ck",
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+ .addr = omap44xx_smartreflex_mpu_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
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+ {
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+ .pa_start = 0x4a0f6000,
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+ .pa_end = 0x4a0f6fff,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_cfg -> spinlock */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_spinlock_hwmod,
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+ .clk = "l4_div_ck",
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+ .addr = omap44xx_spinlock_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
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+ {
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+ .pa_start = 0x4a318000,
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+ .pa_end = 0x4a31807f,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_wkup -> timer1 */
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+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
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+ .master = &omap44xx_l4_wkup_hwmod,
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+ .slave = &omap44xx_timer1_hwmod,
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+ .clk = "l4_wkup_clk_mux_ck",
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+ .addr = omap44xx_timer1_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
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