waterDataDiscreteRateMining varianceMemoryDefinition.h 张婷 commit at 2021-03-05

waterDataDiscreteRateMining/dataSharedMemory/varianceMemoryDefinition.h

@@ -137,3 +137,143 @@
 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
+
+#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
+#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
+#define CICR_VBA_MASK           ((uint)0x000000e0)      /* Vector Base Address */
+#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
+
+
+/*****************************************************************
+       Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
+*****************************************************************/
+
+#define INTR_PIO_PC0    0x80000000      /* parallel I/O C bit 0 */
+#define INTR_SCC1       0x40000000      /* SCC port 1 */
+#define INTR_SCC2       0x20000000      /* SCC port 2 */
+#define INTR_SCC3       0x10000000      /* SCC port 3 */
+#define INTR_SCC4       0x08000000      /* SCC port 4 */
+#define INTR_PIO_PC1    0x04000000      /* parallel i/o C bit 1 */
+#define INTR_TIMER1     0x02000000      /* timer 1 */
+#define INTR_PIO_PC2    0x01000000      /* parallel i/o C bit 2 */
+#define INTR_PIO_PC3    0x00800000      /* parallel i/o C bit 3 */
+#define INTR_SDMA_BERR  0x00400000      /* SDMA channel bus error */
+#define INTR_DMA1       0x00200000      /* idma 1 */
+#define INTR_DMA2       0x00100000      /* idma 2 */
+#define INTR_TIMER2     0x00040000      /* timer 2 */
+#define INTR_CP_TIMER   0x00020000      /* CP timer */
+#define INTR_PIP_STATUS 0x00010000      /* PIP status */
+#define INTR_PIO_PC4    0x00008000      /* parallel i/o C bit 4 */
+#define INTR_PIO_PC5    0x00004000      /* parallel i/o C bit 5 */
+#define INTR_TIMER3     0x00001000      /* timer 3 */
+#define INTR_PIO_PC6    0x00000800      /* parallel i/o C bit 6 */
+#define INTR_PIO_PC7    0x00000400      /* parallel i/o C bit 7 */
+#define INTR_PIO_PC8    0x00000200      /* parallel i/o C bit 8 */
+#define INTR_TIMER4     0x00000080      /* timer 4 */
+#define INTR_PIO_PC9    0x00000040      /* parallel i/o C bit 9 */
+#define INTR_SCP        0x00000020      /* SCP */
+#define INTR_SMC1       0x00000010      /* SMC 1 */
+#define INTR_SMC2       0x00000008      /* SMC 2 */
+#define INTR_PIO_PC10   0x00000004      /* parallel i/o C bit 10 */
+#define INTR_PIO_PC11   0x00000002      /* parallel i/o C bit 11 */
+#define INTR_ERR        0x00000001      /* error */
+
+
+/*****************************************************************
+        CPM Interrupt vector encodings (MC68360UM p. 7-376)
+*****************************************************************/
+
+#define CPMVEC_NR		32
+#define CPMVEC_PIO_PC0		0x1f
+#define CPMVEC_SCC1		0x1e
+#define CPMVEC_SCC2		0x1d
+#define CPMVEC_SCC3		0x1c
+#define CPMVEC_SCC4		0x1b
+#define CPMVEC_PIO_PC1		0x1a
+#define CPMVEC_TIMER1		0x19
+#define CPMVEC_PIO_PC2		0x18
+#define CPMVEC_PIO_PC3		0x17
+#define CPMVEC_SDMA_CB_ERR	0x16
+#define CPMVEC_IDMA1		0x15
+#define CPMVEC_IDMA2		0x14
+#define CPMVEC_RESERVED3	0x13
+#define CPMVEC_TIMER2		0x12
+#define CPMVEC_RISCTIMER	0x11
+#define CPMVEC_RESERVED2	0x10
+#define CPMVEC_PIO_PC4		0x0f
+#define CPMVEC_PIO_PC5		0x0e
+#define CPMVEC_TIMER3		0x0c
+#define CPMVEC_PIO_PC6		0x0b
+#define CPMVEC_PIO_PC7		0x0a
+#define CPMVEC_PIO_PC8		0x09
+#define CPMVEC_RESERVED1	0x08
+#define CPMVEC_TIMER4		0x07
+#define CPMVEC_PIO_PC9		0x06
+#define CPMVEC_SPI		0x05
+#define CPMVEC_SMC1		0x04
+#define CPMVEC_SMC2		0x03
+#define CPMVEC_PIO_PC10		0x02
+#define CPMVEC_PIO_PC11		0x01
+#define CPMVEC_ERROR		0x00
+
+/* #define CPMVEC_PIO_PC0		((ushort)0x1f) */
+/* #define CPMVEC_SCC1		((ushort)0x1e) */
+/* #define CPMVEC_SCC2		((ushort)0x1d) */
+/* #define CPMVEC_SCC3		((ushort)0x1c) */
+/* #define CPMVEC_SCC4		((ushort)0x1b) */
+/* #define CPMVEC_PIO_PC1		((ushort)0x1a) */
+/* #define CPMVEC_TIMER1		((ushort)0x19) */
+/* #define CPMVEC_PIO_PC2		((ushort)0x18) */
+/* #define CPMVEC_PIO_PC3		((ushort)0x17) */
+/* #define CPMVEC_SDMA_CB_ERR	((ushort)0x16) */
+/* #define CPMVEC_IDMA1		((ushort)0x15) */
+/* #define CPMVEC_IDMA2		((ushort)0x14) */
+/* #define CPMVEC_RESERVED3	((ushort)0x13) */
+/* #define CPMVEC_TIMER2		((ushort)0x12) */
+/* #define CPMVEC_RISCTIMER	((ushort)0x11) */
+/* #define CPMVEC_RESERVED2	((ushort)0x10) */
+/* #define CPMVEC_PIO_PC4		((ushort)0x0f) */
+/* #define CPMVEC_PIO_PC5		((ushort)0x0e) */
+/* #define CPMVEC_TIMER3		((ushort)0x0c) */
+/* #define CPMVEC_PIO_PC6		((ushort)0x0b) */
+/* #define CPMVEC_PIO_PC7		((ushort)0x0a) */
+/* #define CPMVEC_PIO_PC8		((ushort)0x09) */
+/* #define CPMVEC_RESERVED1	((ushort)0x08) */
+/* #define CPMVEC_TIMER4		((ushort)0x07) */
+/* #define CPMVEC_PIO_PC9		((ushort)0x06) */
+/* #define CPMVEC_SPI		((ushort)0x05) */
+/* #define CPMVEC_SMC1		((ushort)0x04) */
+/* #define CPMVEC_SMC2		((ushort)0x03) */
+/* #define CPMVEC_PIO_PC10		((ushort)0x02) */
+/* #define CPMVEC_PIO_PC11		((ushort)0x01) */
+/* #define CPMVEC_ERROR		((ushort)0x00) */
+
+
+/*****************************************************************
+ *        PIO control registers
+ *****************************************************************/
+
+/* Port A - See 360UM p. 7-358
+ * 
+ *  Note that most of these pins have alternate functions
+ */
+
+
+/* The macros are nice, but there are all sorts of references to 1-indexed
+ * facilities on the 68360... */
+/* #define PA_RXD(n)	((ushort)(0x01<<(2*n))) */
+/* #define PA_TXD(n)	((ushort)(0x02<<(2*n))) */
+
+#define PA_RXD1		((ushort)0x0001)
+#define PA_TXD1		((ushort)0x0002)
+#define PA_RXD2		((ushort)0x0004)
+#define PA_TXD2		((ushort)0x0008)
+#define PA_RXD3		((ushort)0x0010)
+#define PA_TXD3		((ushort)0x0020)
+#define PA_RXD4		((ushort)0x0040)
+#define PA_TXD4		((ushort)0x0080)
+
+#define PA_CLK1		((ushort)0x0100)
+#define PA_CLK2		((ushort)0x0200)
+#define PA_CLK3		((ushort)0x0400)
+#define PA_CLK4		((ushort)0x0800)