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@@ -2698,3 +2698,59 @@
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SEC Registers
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SEC Registers
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========================= */
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========================= */
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/* ------------------------------------------------------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------------------------------------------------
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+ SEC Core Interface (SCI) Register Definitions
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+ ------------------------------------------------------------------------------------------------------------------------ */
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+
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+#define SEC_SCI_BASE 0xFFCA4400
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+#define SEC_SCI_OFF 0x40
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+#define SEC_CCTL 0x0 /* SEC Core Control Register n */
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+#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
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+#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
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+#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
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+#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
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+#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
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+#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
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+#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
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+
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+#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
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+#define bfin_write_SEC_SCI(n, reg, val) \
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+ bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
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+
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+/* ------------------------------------------------------------------------------------------------------------------------
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+ SEC Fault Management Interface (SFI) Register Definitions
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+ ------------------------------------------------------------------------------------------------------------------------ */
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+#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
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+#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
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+#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
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+#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
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+#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
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+#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
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+#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
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+#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
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+#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
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+#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
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+
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+/* ------------------------------------------------------------------------------------------------------------------------
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+ SEC Global Register Definitions
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+ ------------------------------------------------------------------------------------------------------------------------ */
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+#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
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+#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
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+#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
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+#define SEC_END 0xFFCA400C /* SEC Global End Register */
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+
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+/* ------------------------------------------------------------------------------------------------------------------------
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+ SEC Source Interface (SSI) Register Definitions
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+ ------------------------------------------------------------------------------------------------------------------------ */
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+#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
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+#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
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