|
|
@@ -301,3 +301,60 @@ titan_init_one_pachip_port(titan_pachip_port *port, int index)
|
|
|
saved_config[index].wsba[2] = port->wsba[2].csr;
|
|
|
saved_config[index].wsm[2] = port->wsm[2].csr;
|
|
|
saved_config[index].tba[2] = port->tba[2].csr;
|
|
|
+
|
|
|
+ saved_config[index].wsba[3] = port->wsba[3].csr;
|
|
|
+ saved_config[index].wsm[3] = port->wsm[3].csr;
|
|
|
+ saved_config[index].tba[3] = port->tba[3].csr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set up the PCI to main memory translation windows.
|
|
|
+ *
|
|
|
+ * Note: Window 3 on Titan is Scatter-Gather ONLY.
|
|
|
+ *
|
|
|
+ * Window 0 is scatter-gather 8MB at 8MB (for isa)
|
|
|
+ * Window 1 is direct access 1GB at 2GB
|
|
|
+ * Window 2 is scatter-gather 1GB at 3GB
|
|
|
+ */
|
|
|
+ hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
|
|
|
+ hose->sg_isa->align_entry = 8; /* 64KB for ISA */
|
|
|
+
|
|
|
+ hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0);
|
|
|
+ hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */
|
|
|
+
|
|
|
+ port->wsba[0].csr = hose->sg_isa->dma_base | 3;
|
|
|
+ port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
|
|
|
+ port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
|
|
|
+
|
|
|
+ port->wsba[1].csr = __direct_map_base | 1;
|
|
|
+ port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;
|
|
|
+ port->tba[1].csr = 0;
|
|
|
+
|
|
|
+ port->wsba[2].csr = hose->sg_pci->dma_base | 3;
|
|
|
+ port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;
|
|
|
+ port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);
|
|
|
+
|
|
|
+ port->wsba[3].csr = 0;
|
|
|
+
|
|
|
+ /* Enable the Monster Window to make DAC pci64 possible. */
|
|
|
+ port->pctl.csr |= pctl_m_mwin;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * If it's an AGP port, initialize agplastwr.
|
|
|
+ */
|
|
|
+ if (titan_query_agp(port))
|
|
|
+ port->port_specific.a.agplastwr.csr = __direct_map_base;
|
|
|
+
|
|
|
+ titan_pci_tbi(hose, 0, -1);
|
|
|
+}
|
|
|
+
|
|
|
+static void __init
|
|
|
+titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
|
|
|
+{
|
|
|
+ titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
|
|
|
+
|
|
|
+ /* Init the ports in hose order... */
|
|
|
+ titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */
|
|
|
+ if (titan_pchip1_present)
|
|
|
+ titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */
|
|
|
+ titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */
|
|
|
+ if (titan_pchip1_present)
|
袁明明