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@@ -1565,3 +1565,156 @@
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#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
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#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
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#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
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+#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
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+#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
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+#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
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+#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
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+#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
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+#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
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+#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
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+#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
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+#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
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+#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
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+#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
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+#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 36 Registers */
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+
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+#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
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+#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
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+#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
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+#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
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+#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
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+#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
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+#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
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+#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
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+#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
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+#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
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+#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
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+#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
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+#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
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+#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
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+#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
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+#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
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+#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
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+#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
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+#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
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+#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
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+#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
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+#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
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+#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
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+#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
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+#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
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+#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
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+#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
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+#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
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+#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
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+#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
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+#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
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+#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 37 Registers */
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+
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+#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
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+#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
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+#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
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+#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
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+#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
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+#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
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+#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
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+#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
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+#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
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+#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
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+#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
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+#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
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+#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
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+#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
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+#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
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+#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
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+#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
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+#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
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+#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
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+#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
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+#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
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+#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
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+#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
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+#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
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+#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
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+#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
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+#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
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+#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
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+#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
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+#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
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+#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
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+#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 38 Registers */
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+
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+#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
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+#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
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+#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
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+#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
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+#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
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+#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
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+#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
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+#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
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+#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
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+#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
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+#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
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+#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
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+#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
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+#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
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+#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
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+#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
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+#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
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+#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
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+#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
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+#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
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+#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
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+#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
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+#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
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+#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
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+#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
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+#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
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+#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
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+#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
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+#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
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+#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
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+#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
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+#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 39 Registers */
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+
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+#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
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+#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
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+#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
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+#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
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+#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
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+#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
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+#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
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+#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
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+#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
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+#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
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+#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
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+#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
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+#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
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+#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
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+#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
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+#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
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+#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
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+#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
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+#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
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+#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
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+#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
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+#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
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+#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
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+#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
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+#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
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袁明明