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@@ -2123,3 +2123,101 @@ static struct pinmux_gpio pinmux_gpios[] = {
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GPIO_FN(MMCD1_4),
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GPIO_FN(MCP_D3_MCP_NAF3), \
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GPIO_FN(MMCD1_3),
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+ GPIO_FN(MCP_D2_MCP_NAF2), \
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+ GPIO_FN(MMCD1_2),
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+ GPIO_FN(MCP_D1_MCP_NAF1), \
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+ GPIO_FN(MMCD1_1),
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+ GPIO_FN(MCP_D0_MCP_NAF0), \
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+ GPIO_FN(MMCD1_0),
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+ GPIO_FN(MCP_NBRSTOUT_),
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+ GPIO_FN(MCP_WE0__MCP_FWE), \
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+ GPIO_FN(MCP_RDWR_MCP_FWE),
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+
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+ /* MSEL2 special cases */
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+ GPIO_FN(TSIF2_TS_XX1),
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+ GPIO_FN(TSIF2_TS_XX2),
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+ GPIO_FN(TSIF2_TS_XX3),
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+ GPIO_FN(TSIF2_TS_XX4),
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+ GPIO_FN(TSIF2_TS_XX5),
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+ GPIO_FN(TSIF1_TS_XX1),
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+ GPIO_FN(TSIF1_TS_XX2),
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+ GPIO_FN(TSIF1_TS_XX3),
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+ GPIO_FN(TSIF1_TS_XX4),
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+ GPIO_FN(TSIF1_TS_XX5),
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+ GPIO_FN(TSIF0_TS_XX1),
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+ GPIO_FN(TSIF0_TS_XX2),
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+ GPIO_FN(TSIF0_TS_XX3),
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+ GPIO_FN(TSIF0_TS_XX4),
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+ GPIO_FN(TSIF0_TS_XX5),
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+ GPIO_FN(MST1_TS_XX1),
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+ GPIO_FN(MST1_TS_XX2),
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+ GPIO_FN(MST1_TS_XX3),
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+ GPIO_FN(MST1_TS_XX4),
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+ GPIO_FN(MST1_TS_XX5),
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+ GPIO_FN(MST0_TS_XX1),
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+ GPIO_FN(MST0_TS_XX2),
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+ GPIO_FN(MST0_TS_XX3),
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+ GPIO_FN(MST0_TS_XX4),
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+ GPIO_FN(MST0_TS_XX5),
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+
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+ /* MSEL3 special cases */
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+ GPIO_FN(SDHI0_VCCQ_MC0_ON),
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+ GPIO_FN(SDHI0_VCCQ_MC0_OFF),
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+ GPIO_FN(DEBUG_MON_VIO),
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+ GPIO_FN(DEBUG_MON_LCDD),
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+ GPIO_FN(LCDC_LCDC0),
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+ GPIO_FN(LCDC_LCDC1),
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+
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+ /* MSEL4 special cases */
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+ GPIO_FN(IRQ9_MEM_INT),
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+ GPIO_FN(IRQ9_MCP_INT),
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+ GPIO_FN(A11),
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+ GPIO_FN(KEYOUT8),
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+ GPIO_FN(TPU4TO3),
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+ GPIO_FN(RESETA_N_PU_ON),
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+ GPIO_FN(RESETA_N_PU_OFF),
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+ GPIO_FN(EDBGREQ_PD),
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+ GPIO_FN(EDBGREQ_PU),
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+
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+ /* Functions with pull-ups */
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+ GPIO_FN(KEYIN0_PU),
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+ GPIO_FN(KEYIN1_PU),
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+ GPIO_FN(KEYIN2_PU),
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+ GPIO_FN(KEYIN3_PU),
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+ GPIO_FN(KEYIN4_PU),
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+ GPIO_FN(KEYIN5_PU),
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+ GPIO_FN(KEYIN6_PU),
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+ GPIO_FN(KEYIN7_PU),
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+ GPIO_FN(SDHICD0_PU),
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+ GPIO_FN(SDHID0_0_PU),
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+ GPIO_FN(SDHID0_1_PU),
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+ GPIO_FN(SDHID0_2_PU),
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+ GPIO_FN(SDHID0_3_PU),
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+ GPIO_FN(SDHICMD0_PU),
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+ GPIO_FN(SDHIWP0_PU),
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+ GPIO_FN(SDHID1_0_PU),
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+ GPIO_FN(SDHID1_1_PU),
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+ GPIO_FN(SDHID1_2_PU),
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+ GPIO_FN(SDHID1_3_PU),
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+ GPIO_FN(SDHICMD1_PU),
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+ GPIO_FN(SDHID2_0_PU),
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+ GPIO_FN(SDHID2_1_PU),
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+ GPIO_FN(SDHID2_2_PU),
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+ GPIO_FN(SDHID2_3_PU),
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+ GPIO_FN(SDHICMD2_PU),
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+ GPIO_FN(MMCCMD0_PU),
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+ GPIO_FN(MMCCMD1_PU),
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+ GPIO_FN(MMCD0_0_PU),
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+ GPIO_FN(MMCD0_1_PU),
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+ GPIO_FN(MMCD0_2_PU),
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+ GPIO_FN(MMCD0_3_PU),
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+ GPIO_FN(MMCD0_4_PU),
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+ GPIO_FN(MMCD0_5_PU),
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+ GPIO_FN(MMCD0_6_PU),
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+ GPIO_FN(MMCD0_7_PU),
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+ GPIO_FN(FSIACK_PU),
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+ GPIO_FN(FSIAILR_PU),
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+ GPIO_FN(FSIAIBT_PU),
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+ GPIO_FN(FSIAISLD_PU),
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+};
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+
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