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+/*
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+ * R8A7740 processor support
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+ *
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+ * Copyright (C) 2011 Renesas Solutions Corp.
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+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/io.h>
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+#include <linux/sh_intc.h>
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+#include <mach/intc.h>
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+#include <mach/irqs.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+
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+/*
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+ * INTCA
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+ */
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+enum {
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+ UNUSED_INTCA = 0,
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+
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+ /* interrupt sources INTCA */
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+ DIRC,
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+ ATAPI,
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+ IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
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+ AP_ARM_COMMTX, AP_ARM_COMMRX,
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+ MFI, MFIS,
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+ BBIF1, BBIF2,
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+ USBHSDMAC,
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+ USBF_OUL_SOF, USBF_IXL_INT,
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+ SGX540,
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+ CMT1_0, CMT1_1, CMT1_2, CMT1_3,
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+ CMT2,
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+ CMT3,
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+ KEYSC,
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+ SCIFA0, SCIFA1, SCIFA2, SCIFA3,
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+ MSIOF2, MSIOF1,
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+ SCIFA4, SCIFA5, SCIFB,
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+ FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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+ SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
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+ SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
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+ AP_ARM_L2CINT,
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+ IRDA,
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+ TPU0,
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+ SCIFA6, SCIFA7,
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+ GbEther,
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+ ICBS0,
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+ DDM,
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+ SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
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+ RWDT0,
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+ DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
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+ DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
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+ DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
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+ DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
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+ DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
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+ DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
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+ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
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+ HDMI,
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+ USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
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+ RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
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+ SPU2_0, SPU2_1,
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+ FSI, FMSI,
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+ HDMI_SSS, HDMI_KEY,
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+ IPMMU,
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+ AP_ARM_CTIIRQ, AP_ARM_PMURQ,
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+ MFIS2,
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+ CPORTR2S,
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+ CMT14, CMT15,
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+ MMCIF_0, MMCIF_1, MMCIF_2,
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+ SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
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+ STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
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+
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+ /* interrupt groups INTCA */
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+ DMAC1_1, DMAC1_2,
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+ DMAC2_1, DMAC2_2,
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+ DMAC3_1, DMAC3_2,
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+ AP_ARM1, AP_ARM2,
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+ SDHI0, SDHI1, SDHI2,
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+ SHWYSTAT,
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+ USBF, USBH1, USBH2,
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+ RSPI, SPU2, FLCTL, IIC1,
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+};
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+
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吉超博