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@@ -0,0 +1,123 @@
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+/*
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+ * Copyright 2008-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef _CDEF_BF538_H
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+#define _CDEF_BF538_H
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+
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+#define bfin_writePTR(addr, val) bfin_write32(addr, val)
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+
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+#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
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+#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
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+#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
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+#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
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+#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
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+#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
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+#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
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+#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
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+#define bfin_read_CHIPID() bfin_read32(CHIPID)
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+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
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+#define bfin_read_SWRST() bfin_read16(SWRST)
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+#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
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+#define bfin_read_SYSCR() bfin_read16(SYSCR)
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+#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
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+#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
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+#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
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+#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
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+#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
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+#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
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+#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
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+#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
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+#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
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+#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
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+#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
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+#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
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+#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
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+#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
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+#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
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+#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
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+#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
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+#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
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+#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
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+#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
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+#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
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+#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
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+#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
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+#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
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+#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
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+#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
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+#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
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+#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
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+#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
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+#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
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+#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
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+#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
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+#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
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+#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
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+#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
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+#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
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+#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
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+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
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+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
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+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
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+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
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+#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
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+#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
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+#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
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+#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
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+#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
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+#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
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+#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
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+#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
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+#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
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+#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
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+#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
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+#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
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+#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
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+#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
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+#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
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+#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
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+#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
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+#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
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+#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
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+#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
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+#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
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+#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
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+#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
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+#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
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+#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
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+#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
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+#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
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+#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
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+#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
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+#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
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+#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
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+#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
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+#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
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+#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
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+#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
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+#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
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+#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
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+#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
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+#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
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+#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
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+#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
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+#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
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+#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
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+#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
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+#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
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+#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
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+#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
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+#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
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+#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
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+#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
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+#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
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+#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
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+#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
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+#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
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+#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
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+#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
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+#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
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+#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
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韩正义
4 years ago