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@@ -473,3 +473,143 @@
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#define S3C2410_MISCCR_USBDEV (0<<3)
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#define S3C2410_MISCCR_USBHOST (1<<3)
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+
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+#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
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+#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
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+#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
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+#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
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+#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
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+#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
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+#define S3C2410_MISCCR_CLK0_MASK (7<<4)
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+
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+#define S3C2412_MISCCR_CLK0_RTC (2<<4)
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+
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+#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
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+#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
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+#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
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+#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
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+#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
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+#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
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+#define S3C2410_MISCCR_CLK1_MASK (7<<8)
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+
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+#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
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+
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+#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
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+#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
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+#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
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+
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+#define S3C2410_MISCCR_nRSTCON (1<<16)
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+
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+#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
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+#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
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+#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
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+#define S3C2410_MISCCR_SDSLEEP (7<<17)
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+
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+#define S3C2416_MISCCR_FLT_I2C (1<<24)
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+#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
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+
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+/* external interrupt control... */
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+/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
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+ * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
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+ * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
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+ *
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+ * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
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+ *
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+ * Samsung datasheet p9-25
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+*/
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+#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
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+#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
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+#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
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+
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+#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
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+#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
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+#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
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+
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+/* interrupt filtering conrrol for EINT16..EINT23 */
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+#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
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+#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
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+#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
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+#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
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+
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+#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
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+#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
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+#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
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+#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
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+
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+/* values for interrupt filtering */
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+#define S3C2410_EINTFLT_PCLK (0x00)
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+#define S3C2410_EINTFLT_EXTCLK (1<<7)
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+#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
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+
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+/* removed EINTxxxx defs from here, not meant for this */
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+
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+/* GSTATUS have miscellaneous information in them
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+ *
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+ * These move between s3c2410 and s3c2412 style systems.
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+ */
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+
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+#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
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+#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
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+#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
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+#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
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+#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
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+
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+#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
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+#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
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+#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
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+#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
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+#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
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+
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+#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
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+#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
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+#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
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+#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
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+#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
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+
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+#define S3C2410_GSTATUS0_nWAIT (1<<3)
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+#define S3C2410_GSTATUS0_NCON (1<<2)
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+#define S3C2410_GSTATUS0_RnB (1<<1)
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+#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
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+
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+#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
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+#define S3C2410_GSTATUS1_2410 (0x32410000)
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+#define S3C2410_GSTATUS1_2412 (0x32412001)
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+#define S3C2410_GSTATUS1_2416 (0x32416003)
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+#define S3C2410_GSTATUS1_2440 (0x32440000)
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+#define S3C2410_GSTATUS1_2442 (0x32440aaa)
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+/* some 2416 CPUs report this value also */
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+#define S3C2410_GSTATUS1_2450 (0x32450003)
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+
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+#define S3C2410_GSTATUS2_WTRESET (1<<2)
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+#define S3C2410_GSTATUS2_OFFRESET (1<<1)
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+#define S3C2410_GSTATUS2_PONRESET (1<<0)
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+
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+/* 2412/2413 sleep configuration registers */
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+
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+#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
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+#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
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+#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
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+#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
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+#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
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+#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
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+
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+/* definitions for each pin bit */
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+#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
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+#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
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+#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
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+#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
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+
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+#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
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+#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
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+#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
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+#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
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+#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
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+#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
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+
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+#define S3C2412_SLPCON_ALL_LOW (0x0)
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+#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
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+#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
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+#define S3C2412_SLPCON_ALL_PULL (0x33333333)
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+
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+#endif /* __ASM_ARCH_REGS_GPIO_H */
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+
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梁凤妮