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@@ -1901,3 +1901,164 @@
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#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
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#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
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#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
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+#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
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+#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
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+#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
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+#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
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+#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
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+#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
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+#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
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+#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
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+#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 45 Registers */
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+
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+#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
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+#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
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+#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
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+#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
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+#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
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+#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
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+#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
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+#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
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+#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
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+#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
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+#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
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+#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
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+#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
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+#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
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+#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
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+#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
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+#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
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+#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
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+#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
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+#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
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+#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
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+#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
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+#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
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+#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
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+#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
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+#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
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+#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
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+#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
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+#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
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+#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
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+#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
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+#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 46 Registers */
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+
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+#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
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+#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
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+#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
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+#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
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+#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
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+#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
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+#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
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+#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
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+#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
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+#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
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+#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
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+#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
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+#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
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+#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
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+#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
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+#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
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+#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
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+#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
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+#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
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+#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
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+#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
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+#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
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+#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
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+#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
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+#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
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+#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
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+#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
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+#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
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+#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
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+#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
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+#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
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+#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
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+
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+
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+/* EPPI1 Registers */
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+
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+
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+/* Port Interrubfin_read_()t 0 Registers (32-bit) */
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+
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+#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
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+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
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+#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
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+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
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+#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
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+#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
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+#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
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+#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
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+#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
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+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
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+#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
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+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
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+#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
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+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
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+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
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+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
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+#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
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+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
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+#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
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+#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
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+
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+/* Port Interrubfin_read_()t 1 Registers (32-bit) */
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+
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+#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
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+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
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+#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
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+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
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+#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
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+#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
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+#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
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+#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
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+#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
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+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
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+#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
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+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
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+#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
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+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
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+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
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+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
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+#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
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+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
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+#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
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+#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
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+
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+/* Port Interrubfin_read_()t 2 Registers (32-bit) */
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+
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+#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
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+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
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+#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
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+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
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+#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
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+#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
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+#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
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+#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
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+#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
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+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
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+#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
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+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
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+#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
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+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
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+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
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+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
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+#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
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+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
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+#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
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+#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
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+
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+/* Port Interrubfin_read_()t 3 Registers (32-bit) */
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+
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+#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
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袁明明