efElectricAgingTrendMining memoryOperation.h 岳彩东 commit at 2020-11-17

efElectricAgingTrendMining/dataSharedMemory/memoryOperation.h

@@ -1074,3 +1074,187 @@
 /* Used by PRM_RSTST */
 #define OMAP4430_SECURE_WDT_RST_SHIFT					4
 #define OMAP4430_SECURE_WDT_RST_MASK					(1 << 4)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_ONSTATE_SHIFT					18
+#define OMAP4430_SL2_MEM_ONSTATE_MASK					(0x3 << 18)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_RETSTATE_SHIFT					9
+#define OMAP4430_SL2_MEM_RETSTATE_MASK					(1 << 9)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_SL2_MEM_STATEST_SHIFT					6
+#define OMAP4430_SL2_MEM_STATEST_MASK					(0x3 << 6)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_SLAVEADDR_SHIFT					0
+#define OMAP4430_SLAVEADDR_MASK						(0x7f << 0)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SLEEP_RBB_SEL_SHIFT					3
+#define OMAP4430_SLEEP_RBB_SEL_MASK					(1 << 3)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_SLPCNT_VALUE_SHIFT					16
+#define OMAP4430_SLPCNT_VALUE_MASK					(0xff << 16)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
+#define OMAP4430_SMPSWAITTIMEMAX_MASK					(0xffff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
+#define OMAP4430_SMPSWAITTIMEMIN_MASK					(0xffff << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT					1
+#define OMAP4430_SMPS_RA_ERR_CORE_MASK					(1 << 1)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT					9
+#define OMAP4430_SMPS_RA_ERR_IVA_MASK					(1 << 9)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT					17
+#define OMAP4430_SMPS_RA_ERR_MPU_MASK					(1 << 17)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT					0
+#define OMAP4430_SMPS_SA_ERR_CORE_MASK					(1 << 0)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT					8
+#define OMAP4430_SMPS_SA_ERR_IVA_MASK					(1 << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT					16
+#define OMAP4430_SMPS_SA_ERR_MPU_MASK					(1 << 16)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT				2
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK				(1 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT				10
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK				(1 << 10)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT				18
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK				(1 << 18)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2EN_SHIFT						0
+#define OMAP4430_SR2EN_MASK						(1 << 0)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_IN_TRANSITION_SHIFT				6
+#define OMAP4430_SR2_IN_TRANSITION_MASK					(1 << 6)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_STATUS_SHIFT					3
+#define OMAP4430_SR2_STATUS_MASK					(0x3 << 3)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2_WTCNT_VALUE_SHIFT					8
+#define OMAP4430_SR2_WTCNT_VALUE_MASK					(0xff << 8)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAMLDO_STATUS_SHIFT					8
+#define OMAP4430_SRAMLDO_STATUS_MASK					(1 << 8)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAM_IN_TRANSITION_SHIFT				9
+#define OMAP4430_SRAM_IN_TRANSITION_MASK				(1 << 9)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_SRMODEEN_SHIFT						4
+#define OMAP4430_SRMODEEN_MASK						(1 << 4)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_COUNT_SHIFT					0
+#define OMAP4430_STABLE_COUNT_MASK					(0x3f << 0)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_PRESCAL_SHIFT					8
+#define OMAP4430_STABLE_PRESCAL_MASK					(0x3 << 8)
+
+/* Used by PRM_LDO_BANDGAP_SETUP */
+#define OMAP4430_STARTUP_COUNT_SHIFT					0
+#define OMAP4430_STARTUP_COUNT_MASK					(0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP4430_STARTUP_COUNT_24_31_SHIFT				24
+#define OMAP4430_STARTUP_COUNT_24_31_MASK				(0xff << 24)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT					20
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK					(0x3 << 20)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT				10
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK					(1 << 10)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM1_MEM_STATEST_SHIFT					8
+#define OMAP4430_TCM1_MEM_STATEST_MASK					(0x3 << 8)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT					22
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK					(0x3 << 22)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT				11
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK					(1 << 11)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM2_MEM_STATEST_SHIFT					10
+#define OMAP4430_TCM2_MEM_STATEST_MASK					(0x3 << 10)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLASS_EMU_RSTST_SHIFT				2
+#define OMAP4430_TESLASS_EMU_RSTST_MASK					(1 << 2)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT				3
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK				(1 << 3)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT				20
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK				(0x3 << 20)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT				10
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK				(1 << 10)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_EDMA_STATEST_SHIFT				8
+#define OMAP4430_TESLA_EDMA_STATEST_MASK				(0x3 << 8)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_ONSTATE_SHIFT					16
+#define OMAP4430_TESLA_L1_ONSTATE_MASK					(0x3 << 16)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_RETSTATE_SHIFT				8
+#define OMAP4430_TESLA_L1_RETSTATE_MASK					(1 << 8)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L1_STATEST_SHIFT					4
+#define OMAP4430_TESLA_L1_STATEST_MASK					(0x3 << 4)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_ONSTATE_SHIFT					18
+#define OMAP4430_TESLA_L2_ONSTATE_MASK					(0x3 << 18)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_RETSTATE_SHIFT				9
+#define OMAP4430_TESLA_L2_RETSTATE_MASK					(1 << 9)
+
+/* Used by PM_TESLA_PWRSTST */