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@@ -1 +1,54 @@
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/*
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+ * DO NOT EDIT THIS FILE
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+ * This file is under version control at
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+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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+ * and can be replaced with that version at any time
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+ * DO NOT EDIT THIS FILE
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+ *
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+ * Copyright 2004-2011 Analog Devices Inc.
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+ * Licensed under the Clear BSD license.
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+ */
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+
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+/* This file should be up to date with:
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+ * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
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+ * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
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+ */
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+
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+#ifndef _MACH_ANOMALY_H_
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+#define _MACH_ANOMALY_H_
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+
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+/* We do not support old silicon - sorry */
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+#if __SILICON_REVISION__ < 0
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+# error will not work on BF526/BF527 silicon version
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+#endif
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+
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+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
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+# define ANOMALY_BF526 1
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+#else
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+# define ANOMALY_BF526 0
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+#endif
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+#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
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+# define ANOMALY_BF527 1
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+#else
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+# define ANOMALY_BF527 0
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+#endif
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+
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+#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
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+#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
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+#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
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+
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+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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+#define ANOMALY_05000074 (1)
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+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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+#define ANOMALY_05000119 (1)
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+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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+#define ANOMALY_05000122 (1)
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+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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+#define ANOMALY_05000245 (1)
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+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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+#define ANOMALY_05000254 (1)
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+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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+#define ANOMALY_05000265 (1)
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+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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+#define ANOMALY_05000310 (1)
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+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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