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@@ -243,3 +243,77 @@
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#define IRQ_PE7 BFIN_PE_IRQ(7)
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#define IRQ_PE7 BFIN_PE_IRQ(7)
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#define IRQ_PE8 BFIN_PE_IRQ(8)
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#define IRQ_PE8 BFIN_PE_IRQ(8)
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#define IRQ_PE9 BFIN_PE_IRQ(9)
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#define IRQ_PE9 BFIN_PE_IRQ(9)
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+#define IRQ_PE10 BFIN_PE_IRQ(10)
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+#define IRQ_PE11 BFIN_PE_IRQ(11)
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+#define IRQ_PE12 BFIN_PE_IRQ(12)
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+#define IRQ_PE13 BFIN_PE_IRQ(13)
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+#define IRQ_PE14 BFIN_PE_IRQ(14)
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+#define IRQ_PE15 BFIN_PE_IRQ(15)
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+
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+#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
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+#define IRQ_PF0 BFIN_PF_IRQ(0)
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+#define IRQ_PF1 BFIN_PF_IRQ(1)
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+#define IRQ_PF2 BFIN_PF_IRQ(2)
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+#define IRQ_PF3 BFIN_PF_IRQ(3)
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+#define IRQ_PF4 BFIN_PF_IRQ(4)
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+#define IRQ_PF5 BFIN_PF_IRQ(5)
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+#define IRQ_PF6 BFIN_PF_IRQ(6)
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+#define IRQ_PF7 BFIN_PF_IRQ(7)
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+#define IRQ_PF8 BFIN_PF_IRQ(8)
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+#define IRQ_PF9 BFIN_PF_IRQ(9)
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+#define IRQ_PF10 BFIN_PF_IRQ(10)
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+#define IRQ_PF11 BFIN_PF_IRQ(11)
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+#define IRQ_PF12 BFIN_PF_IRQ(12)
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+#define IRQ_PF13 BFIN_PF_IRQ(13)
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+#define IRQ_PF14 BFIN_PF_IRQ(14)
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+#define IRQ_PF15 BFIN_PF_IRQ(15)
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+
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+#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
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+#define IRQ_PG0 BFIN_PG_IRQ(0)
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+#define IRQ_PG1 BFIN_PG_IRQ(1)
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+#define IRQ_PG2 BFIN_PG_IRQ(2)
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+#define IRQ_PG3 BFIN_PG_IRQ(3)
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+#define IRQ_PG4 BFIN_PG_IRQ(4)
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+#define IRQ_PG5 BFIN_PG_IRQ(5)
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+#define IRQ_PG6 BFIN_PG_IRQ(6)
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+#define IRQ_PG7 BFIN_PG_IRQ(7)
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+#define IRQ_PG8 BFIN_PG_IRQ(8)
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+#define IRQ_PG9 BFIN_PG_IRQ(9)
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+#define IRQ_PG10 BFIN_PG_IRQ(10)
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+#define IRQ_PG11 BFIN_PG_IRQ(11)
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+#define IRQ_PG12 BFIN_PG_IRQ(12)
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+#define IRQ_PG13 BFIN_PG_IRQ(13)
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+#define IRQ_PG14 BFIN_PG_IRQ(14)
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+#define IRQ_PG15 BFIN_PG_IRQ(15)
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+
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+#define GPIO_IRQ_BASE IRQ_PA0
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+
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+#define NR_MACH_IRQS (IRQ_PG15 + 1)
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+
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+#define SEC_SCTL_PRIO_OFFSET 8
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+
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+#ifndef __ASSEMBLY__
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+#include <linux/types.h>
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+
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+extern u8 sec_int_priority[];
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+
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+/*
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+ * bfin pint registers layout
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+ */
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+struct bfin_pint_regs {
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+ u32 mask_set;
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+ u32 mask_clear;
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+ u32 request;
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+ u32 assign;
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+ u32 edge_set;
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+ u32 edge_clear;
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+ u32 invert_set;
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+ u32 invert_clear;
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+ u32 pinstate;
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+ u32 latch;
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+ u32 __pad0[2];
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+};
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+
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+#endif
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+
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+#endif
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