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@@ -136,3 +136,108 @@
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#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
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#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
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+/* Used by PRM_VC_CFG_CHANNEL */
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+#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
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+#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
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+
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+/* Used by PRM_VC_CFG_CHANNEL */
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+#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
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+#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
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+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
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+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
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+
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+/* Used by PM_CORE_PWRSTST */
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+#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
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+#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
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+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
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+
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+/* Used by PM_CORE_PWRSTCTRL */
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+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
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+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
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+
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+/* Used by PM_CORE_PWRSTST */
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+#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
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+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
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+
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+/* Used by REVISION_PRM */
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+#define OMAP4430_CUSTOM_SHIFT 6
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+#define OMAP4430_CUSTOM_MASK (0x3 << 6)
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+
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+/* Used by PRM_VC_VAL_BYPASS */
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+#define OMAP4430_DATA_SHIFT 16
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+#define OMAP4430_DATA_MASK (0xff << 16)
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+
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+/* Used by PRM_DEVICE_OFF_CTRL */
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+#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
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+#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
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+
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+/* Used by PRM_VC_CFG_I2C_MODE */
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+#define OMAP4430_DFILTEREN_SHIFT 6
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+#define OMAP4430_DFILTEREN_MASK (1 << 6)
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+
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+/*
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+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
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+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
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+ */
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+#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
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+#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
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+
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+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
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+#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
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+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
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+
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+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
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+#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
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+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
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+
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+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
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+#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
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+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
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+
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+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
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+#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
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+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
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+
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+/* Used by PRM_IRQENABLE_MPU */
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+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
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+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
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+
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+/* Used by PRM_IRQSTATUS_MPU */
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+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
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+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
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+
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+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
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+#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
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+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
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+
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+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
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+#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
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+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
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+
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+/* Used by PRM_IRQENABLE_MPU */
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+#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
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+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
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+
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+/* Used by PRM_IRQSTATUS_MPU */
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+#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
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+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
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+
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+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
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+#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
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+#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
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+
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+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
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+#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
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+#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
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+
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+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
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+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
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