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@@ -549,3 +549,131 @@
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PM_POP(4, ICPLB_ADDR14)
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PM_POP(3, ICPLB_ADDR13)
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PM_POP(2, ICPLB_ADDR12)
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+ PM_POP(1, ICPLB_ADDR11)
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+ PM_POP(0, ICPLB_ADDR10)
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+ PM_POP_SYNC(13)
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+ PM_POP(13, ICPLB_ADDR9)
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+ PM_POP(12, ICPLB_ADDR8)
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+ PM_POP(11, ICPLB_ADDR7)
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+ PM_POP(10, ICPLB_ADDR6)
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+ PM_POP(9, ICPLB_ADDR5)
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+ PM_POP(8, ICPLB_ADDR4)
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+ PM_POP(7, ICPLB_ADDR3)
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+ PM_POP(6, ICPLB_ADDR2)
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+ PM_POP(5, ICPLB_ADDR1)
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+ PM_POP(4, ICPLB_ADDR0)
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+
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+ /* DCPLB Data */
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+ FP = I2;
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+ PM_POP(3, DCPLB_DATA15)
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+ PM_POP(2, DCPLB_DATA14)
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+ PM_POP(1, DCPLB_DATA13)
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+ PM_POP(0, DCPLB_DATA12)
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+ PM_POP_SYNC(13)
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+ PM_POP(13, DCPLB_DATA11)
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+ PM_POP(12, DCPLB_DATA10)
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+ PM_POP(11, DCPLB_DATA9)
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+ PM_POP(10, DCPLB_DATA8)
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+ PM_POP(9, DCPLB_DATA7)
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+ PM_POP(8, DCPLB_DATA6)
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+ PM_POP(7, DCPLB_DATA5)
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+ PM_POP(6, DCPLB_DATA4)
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+ PM_POP(5, DCPLB_DATA3)
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+ PM_POP(4, DCPLB_DATA2)
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+ PM_POP(3, DCPLB_DATA1)
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+ PM_POP(2, DCPLB_DATA0)
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+
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+ /* DCPLB Addr */
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+ FP = I1;
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+ PM_POP(1, DCPLB_ADDR15)
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+ PM_POP(0, DCPLB_ADDR14)
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+ PM_POP_SYNC(13)
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+ PM_POP(13, DCPLB_ADDR13)
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+ PM_POP(12, DCPLB_ADDR12)
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+ PM_POP(11, DCPLB_ADDR11)
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+ PM_POP(10, DCPLB_ADDR10)
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+ PM_POP(9, DCPLB_ADDR9)
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+ PM_POP(8, DCPLB_ADDR8)
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+ PM_POP(7, DCPLB_ADDR7)
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+ PM_POP(6, DCPLB_ADDR6)
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+ PM_POP(5, DCPLB_ADDR5)
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+ PM_POP(4, DCPLB_ADDR4)
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+ PM_POP(3, DCPLB_ADDR3)
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+ PM_POP(2, DCPLB_ADDR2)
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+ PM_POP(1, DCPLB_ADDR1)
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+ PM_POP(0, DCPLB_ADDR0)
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+
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+
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+ /* Misc non-contiguous registers */
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+
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+ /* icache & dcache will enable later
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+ drop IMEM_CONTROL, DMEM_CONTROL pop
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+ */
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+ FP = I0;
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+ PM_POP_SYNC(2)
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+ PM_CORE_POP(2, TBUFCTL)
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+ PM_CORE_POP(1, IMEM_CONTROL)
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+ PM_CORE_POP(0, DMEM_CONTROL)
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+
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+ /* Core Timer */
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+ FP = B3;
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+ R0 = 0x1;
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+ [FP - 0xC] = R0;
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+
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+ PM_POP_SYNC(13)
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+ FP = B3;
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+ PM_POP(13, TCOUNT)
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+ PM_POP(12, TSCALE)
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+ PM_POP(11, TPERIOD)
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+ PM_POP(10, TCNTL)
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+
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+ /* CEC */
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+ FP = B2;
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+ PM_POP(9, IPRIO)
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+ PM_POP(8, ILAT)
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+ FP += -4; /* IPEND */
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+ PM_POP(7, IMASK)
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+
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+ /* Event Vectors */
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+ FP = B1;
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+ PM_POP(6, EVT15)
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+ PM_POP(5, EVT14)
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+ PM_POP(4, EVT13)
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+ PM_POP(3, EVT12)
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+ PM_POP(2, EVT11)
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+ PM_POP(1, EVT10)
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+ PM_POP(0, EVT9)
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+ PM_POP_SYNC(5)
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+ PM_POP(5, EVT8)
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+ PM_POP(4, EVT7)
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+ PM_POP(3, EVT6)
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+ PM_POP(2, EVT5)
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+ FP += -4; /* EVT4 */
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+ PM_POP(1, EVT3)
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+ PM_POP(0, EVT2)
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+ .endm
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+#endif
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+
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+#include <mach/pll.h>
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+
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+/* PLL_CTL Masks */
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+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
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+#define PLL_OFF 0x0002 /* PLL Not Powered */
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+#define STOPCK 0x0008 /* Core Clock Off */
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+#define PDWN 0x0020 /* Enter Deep Sleep Mode */
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+#ifdef __ADSPBF539__
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+# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
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+# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
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+#else
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+# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
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+# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
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+#endif
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+#define BYPASS 0x0100 /* Bypass the PLL */
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+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
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+#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
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+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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+
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+/* PLL_DIV Masks */
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+#define SSEL 0x000F /* System Select */
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+#define CSEL 0x0030 /* Core Select */
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+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
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