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@@ -2500,3 +2500,197 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap36xx_sr1_hwmod,
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.clk = "sr_l4_ick",
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+ .addr = omap3_sr1_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* L4 CORE -> SR1 interface */
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+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
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+ {
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+ .pa_start = OMAP34XX_SR2_BASE,
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+ .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT,
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+ },
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+ { }
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+};
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+
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+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap34xx_sr2_hwmod,
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+ .clk = "sr_l4_ick",
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+ .addr = omap3_sr2_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap36xx_sr2_hwmod,
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+ .clk = "sr_l4_ick",
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+ .addr = omap3_sr2_addr_space,
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+ .user = OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
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+ {
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+ .pa_start = OMAP34XX_HSUSB_OTG_BASE,
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+ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_core -> usbhsotg */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &omap3xxx_usbhsotg_hwmod,
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+ .clk = "l4_ick",
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+ .addr = omap3xxx_usbhsotg_addrs,
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+ .user = OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
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+ {
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+ .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
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+ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_core -> usbhsotg */
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+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
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+ .master = &omap3xxx_l4_core_hwmod,
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+ .slave = &am35xx_usbhsotg_hwmod,
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+ .clk = "hsotgusb_ick",
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+ .addr = am35xx_usbhsotg_addrs,
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+ .user = OCP_USER_MPU,
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+};
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+
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+/* L4_WKUP -> L4_SEC interface */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
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+ .master = &omap3xxx_l4_wkup_hwmod,
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+ .slave = &omap3xxx_l4_sec_hwmod,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* IVA2 <- L3 interface */
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+static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
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+ .master = &omap3xxx_l3_main_hwmod,
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+ .slave = &omap3xxx_iva_hwmod,
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+ .clk = "core_l3_ick",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
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+ {
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+ .pa_start = 0x48318000,
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+ .pa_end = 0x48318000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_wkup -> timer1 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
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+ .master = &omap3xxx_l4_wkup_hwmod,
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+ .slave = &omap3xxx_timer1_hwmod,
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+ .clk = "gpt1_ick",
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+ .addr = omap3xxx_timer1_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
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+ {
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+ .pa_start = 0x49032000,
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+ .pa_end = 0x49032000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> timer2 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_timer2_hwmod,
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+ .clk = "gpt2_ick",
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+ .addr = omap3xxx_timer2_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
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+ {
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+ .pa_start = 0x49034000,
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+ .pa_end = 0x49034000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> timer3 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_timer3_hwmod,
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+ .clk = "gpt3_ick",
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+ .addr = omap3xxx_timer3_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
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+ {
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+ .pa_start = 0x49036000,
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+ .pa_end = 0x49036000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> timer4 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_timer4_hwmod,
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+ .clk = "gpt4_ick",
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+ .addr = omap3xxx_timer4_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
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+ {
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+ .pa_start = 0x49038000,
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+ .pa_end = 0x49038000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> timer5 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_timer5_hwmod,
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+ .clk = "gpt5_ick",
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+ .addr = omap3xxx_timer5_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
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+ {
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+ .pa_start = 0x4903A000,
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+ .pa_end = 0x4903A000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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+ },
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+ { }
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+};
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+
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+/* l4_per -> timer6 */
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+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
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+ .master = &omap3xxx_l4_per_hwmod,
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+ .slave = &omap3xxx_timer6_hwmod,
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+ .clk = "gpt6_ick",
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+ .addr = omap3xxx_timer6_addrs,
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
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+ {
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+ .pa_start = 0x4903C000,
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+ .pa_end = 0x4903C000 + SZ_1K - 1,
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+ .flags = ADDR_TYPE_RT
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