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@@ -89,3 +89,141 @@
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#define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0)
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#define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1)
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#define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2)
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+#define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU)
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+#define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI)
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+#define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C)
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+#define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME)
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+#define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC)
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+#define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS)
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+#define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD)
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+#define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB)
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+#define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0)
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+#define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1)
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+#define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2)
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+#define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3)
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+#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
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+#define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO)
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+#define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0)
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+#define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1)
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+#define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2)
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+#define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3)
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+#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
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+#define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC)
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+
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+/*********************************
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+ * System functions *
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+ *********************************/
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+
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+/* Registers */
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+#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
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+#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
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+#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
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+#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
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+
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+/* FIXME: Docs are not consistent */
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+/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
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+#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
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+
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+#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
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+#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
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+#define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70)
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+#define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200)
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+#define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204)
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+#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
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+#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
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+
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+/* Bits */
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+#define NETX_SYSTEM_RES_CR_RSTIN (1<<0)
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+#define NETX_SYSTEM_RES_CR_WDG_RES (1<<1)
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+#define NETX_SYSTEM_RES_CR_HOST_RES (1<<2)
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+#define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3)
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+#define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4)
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+#define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5)
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+#define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6)
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+#define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7)
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+#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
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+#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
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+#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
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+#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
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+#define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20)
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+#define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21)
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+#define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22)
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+#define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23)
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+#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24)
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+#define NETX_SYSTEM_RES_CR_RSTOUT (1<<25)
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+#define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26)
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+
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+#define PHY_CONTROL_RESET (1<<31)
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+#define PHY_CONTROL_SIM_BYP (1<<30)
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+#define PHY_CONTROL_CLK_XLATIN (1<<29)
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+#define PHY_CONTROL_PHY1_EN (1<<21)
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+#define PHY_CONTROL_PHY1_NP_MSG_CODE
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+#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17)
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+#define PHY_CONTROL_PHY1_FIXMODE (1<<16)
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+#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13)
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+#define PHY_CONTROL_PHY0_EN (1<<12)
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+#define PHY_CONTROL_PHY0_NP_MSG_CODE
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+#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8)
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+#define PHY_CONTROL_PHY0_FIXMODE (1<<7)
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+#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4)
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+#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
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+
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+#define PHY_MODE_10BASE_T_HALF 0
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+#define PHY_MODE_10BASE_T_FULL 1
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+#define PHY_MODE_100BASE_TX_FX_FULL 2
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+#define PHY_MODE_100BASE_TX_FX_HALF 3
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+#define PHY_MODE_100BASE_TX_HALF 4
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+#define PHY_MODE_REPEATER 5
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+#define PHY_MODE_POWER_DOWN 6
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+#define PHY_MODE_ALL 7
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+
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+/* Bits */
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+#define VECT_CNTL_ENABLE (1 << 5)
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+
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+/*******************************
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+ * GPIO and timer module *
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+ *******************************/
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+
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+/* Registers */
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+#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
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+#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
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+#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
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+#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
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+#define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2))
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+#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
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+#define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc)
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+#define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0)
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+#define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4)
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+#define NETX_GPIO_LINE NETX_GPIO_REG(0xc8)
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+#define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0)
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+
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+/* Bits */
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+#define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0)
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+#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1)
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+#define NETX_GPIO_CFG_IOCFG_GP_UART (0x2)
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+#define NETX_GPIO_CFG_INV (1<<2)
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+#define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3)
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+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
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+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
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+#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3)
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+#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)
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+#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5)
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+#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5)
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+#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5)
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+#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5)
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+#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5)
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+
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+#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)
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+#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1)
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+#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2)
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+#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3)
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+#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4)
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+#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5)
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+#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6)
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+#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
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+
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+#define GPIO_BIT(gpio) (1<<(gpio))
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+#define COUNTER_BIT(counter) ((1<<16)<<(counter))
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+
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+/*******************************
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+ * PIO *
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