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@@ -1690,3 +1690,136 @@ typedef union pal_itr_valid_u {
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priv_level_valid : 1,
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priv_level_valid : 1,
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dirty_bit_valid : 1,
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dirty_bit_valid : 1,
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mem_attr_valid : 1,
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mem_attr_valid : 1,
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+ reserved : 60;
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+ } pal_tr_valid_s;
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+} pal_tr_valid_u_t;
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+
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+/* Read a translation register */
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+static inline s64
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+ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
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+ if (tr_valid)
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+ tr_valid->piv_val = iprv.v0;
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+ return iprv.status;
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+}
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+
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+/*
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+ * PAL_PREFETCH_VISIBILITY transaction types
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+ */
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+#define PAL_VISIBILITY_VIRTUAL 0
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+#define PAL_VISIBILITY_PHYSICAL 1
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+
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+/*
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+ * PAL_PREFETCH_VISIBILITY return codes
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+ */
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+#define PAL_VISIBILITY_OK 1
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+#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
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+#define PAL_VISIBILITY_INVAL_ARG -2
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+#define PAL_VISIBILITY_ERROR -3
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+
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+static inline s64
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+ia64_pal_prefetch_visibility (s64 trans_type)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
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+ return iprv.status;
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+}
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+
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+/* data structure for getting information on logical to physical mappings */
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+typedef union pal_log_overview_u {
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+ struct {
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+ u64 num_log :16, /* Total number of logical
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+ * processors on this die
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+ */
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+ tpc :8, /* Threads per core */
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+ reserved3 :8, /* Reserved */
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+ cpp :8, /* Cores per processor */
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+ reserved2 :8, /* Reserved */
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+ ppid :8, /* Physical processor ID */
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+ reserved1 :8; /* Reserved */
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+ } overview_bits;
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+ u64 overview_data;
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+} pal_log_overview_t;
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+
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+typedef union pal_proc_n_log_info1_u{
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+ struct {
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+ u64 tid :16, /* Thread id */
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+ reserved2 :16, /* Reserved */
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+ cid :16, /* Core id */
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+ reserved1 :16; /* Reserved */
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+ } ppli1_bits;
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+ u64 ppli1_data;
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+} pal_proc_n_log_info1_t;
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+
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+typedef union pal_proc_n_log_info2_u {
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+ struct {
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+ u64 la :16, /* Logical address */
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+ reserved :48; /* Reserved */
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+ } ppli2_bits;
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+ u64 ppli2_data;
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+} pal_proc_n_log_info2_t;
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+
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+typedef struct pal_logical_to_physical_s
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+{
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+ pal_log_overview_t overview;
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+ pal_proc_n_log_info1_t ppli1;
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+ pal_proc_n_log_info2_t ppli2;
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+} pal_logical_to_physical_t;
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+
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+#define overview_num_log overview.overview_bits.num_log
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+#define overview_tpc overview.overview_bits.tpc
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+#define overview_cpp overview.overview_bits.cpp
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+#define overview_ppid overview.overview_bits.ppid
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+#define log1_tid ppli1.ppli1_bits.tid
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+#define log1_cid ppli1.ppli1_bits.cid
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+#define log2_la ppli2.ppli2_bits.la
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+
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+/* Get information on logical to physical processor mappings. */
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+static inline s64
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+ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
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+{
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+ struct ia64_pal_retval iprv;
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+
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+ PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
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+
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+ if (iprv.status == PAL_STATUS_SUCCESS)
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+ {
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+ mapping->overview.overview_data = iprv.v0;
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+ mapping->ppli1.ppli1_data = iprv.v1;
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+ mapping->ppli2.ppli2_data = iprv.v2;
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+ }
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+
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+ return iprv.status;
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+}
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+
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+typedef struct pal_cache_shared_info_s
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+{
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+ u64 num_shared;
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+ pal_proc_n_log_info1_t ppli1;
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+ pal_proc_n_log_info2_t ppli2;
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+} pal_cache_shared_info_t;
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+
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+/* Get information on logical to physical processor mappings. */
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+static inline s64
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+ia64_pal_cache_shared_info(u64 level,
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+ u64 type,
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+ u64 proc_number,
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+ pal_cache_shared_info_t *info)
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+{
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+ struct ia64_pal_retval iprv;
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+
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+ PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
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+
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+ if (iprv.status == PAL_STATUS_SUCCESS) {
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+ info->num_shared = iprv.v0;
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+ info->ppli1.ppli1_data = iprv.v1;
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+ info->ppli2.ppli2_data = iprv.v2;
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+ }
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+
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+ return iprv.status;
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+}
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+#endif /* __ASSEMBLY__ */
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+
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+#endif /* _ASM_IA64_PAL_H */
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