/*
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#ifndef __MACH_BOARD_CNS3XXXH
#define __MACH_BOARD_CNS3XXXH

/*
 * Memory map
 */
#define CNS3XXX_FLASH_BASE			0x10000000	/* Flash/SRAM Memory Bank 0 */
#define CNS3XXX_FLASH_SIZE			SZ_256M

#define CNS3XXX_DDR2SDRAM_BASE			0x20000000	/* DDR2 SDRAM Memory */

#define CNS3XXX_SPI_FLASH_BASE			0x60000000	/* SPI Serial Flash Memory */

#define CNS3XXX_SWITCH_BASE			0x70000000	/* Switch and HNAT Control */
#define CNS3XXX_SWITCH_BASE_VIRT		0xFFF00000

#define CNS3XXX_PPE_BASE			0x70001000	/* HANT	*/
#define CNS3XXX_PPE_BASE_VIRT			0xFFF50000

#define CNS3XXX_EMBEDDED_SRAM_BASE		0x70002000	/* HANT Embedded SRAM */
#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT		0xFFF60000

#define CNS3XXX_SSP_BASE			0x71000000	/* Synchronous Serial Port - SPI/PCM/I2C */
#define CNS3XXX_SSP_BASE_VIRT			0xFFF01000

#define CNS3XXX_DMC_BASE			0x72000000	/* DMC Control (DDR2 SDRAM) */
#define CNS3XXX_DMC_BASE_VIRT			0xFFF02000

#define CNS3XXX_SMC_BASE			0x73000000	/* SMC Control */
#define CNS3XXX_SMC_BASE_VIRT			0xFFF03000

#define SMC_MEMC_STATUS_OFFSET			0x000
#define SMC_MEMIF_CFG_OFFSET			0x004
#define SMC_MEMC_CFG_SET_OFFSET			0x008
#define SMC_MEMC_CFG_CLR_OFFSET			0x00C
#define SMC_DIRECT_CMD_OFFSET			0x010
#define SMC_SET_CYCLES_OFFSET			0x014
#define SMC_SET_OPMODE_OFFSET			0x018
#define SMC_REFRESH_PERIOD_0_OFFSET		0x020
#define SMC_REFRESH_PERIOD_1_OFFSET		0x024
#define SMC_SRAM_CYCLES0_0_OFFSET		0x100
#define SMC_NAND_CYCLES0_0_OFFSET		0x100
#define SMC_OPMODE0_0_OFFSET			0x104
#define SMC_SRAM_CYCLES0_1_OFFSET		0x120
#define SMC_NAND_CYCLES0_1_OFFSET		0x120
#define SMC_OPMODE0_1_OFFSET			0x124
#define SMC_USER_STATUS_OFFSET			0x200
#define SMC_USER_CONFIG_OFFSET			0x204
#define SMC_ECC_STATUS_OFFSET			0x300
#define SMC_ECC_MEMCFG_OFFSET			0x304
#define SMC_ECC_MEMCOMMAND1_OFFSET		0x308
#define SMC_ECC_MEMCOMMAND2_OFFSET		0x30C
#define SMC_ECC_ADDR0_OFFSET			0x310
#define SMC_ECC_ADDR1_OFFSET			0x314
#define SMC_ECC_VALUE0_OFFSET			0x318
#define SMC_ECC_VALUE1_OFFSET			0x31C
#define SMC_ECC_VALUE2_OFFSET			0x320
#define SMC_ECC_VALUE3_OFFSET			0x324
#define SMC_PERIPH_ID_0_OFFSET			0xFE0
#define SMC_PERIPH_ID_1_OFFSET			0xFE4
#define SMC_PERIPH_ID_2_OFFSET			0xFE8
#define SMC_PERIPH_ID_3_OFFSET			0xFEC
#define SMC_PCELL_ID_0_OFFSET			0xFF0
#define SMC_PCELL_ID_1_OFFSET			0xFF4
#define SMC_PCELL_ID_2_OFFSET			0xFF8
#define SMC_PCELL_ID_3_OFFSET			0xFFC

#define CNS3XXX_GPIOA_BASE			0x74000000	/* GPIO port A */
#define CNS3XXX_GPIOA_BASE_VIRT			0xFFF04000

#define CNS3XXX_GPIOB_BASE			0x74800000	/* GPIO port B */
#define CNS3XXX_GPIOB_BASE_VIRT			0xFFF05000

#define CNS3XXX_RTC_BASE			0x75000000	/* Real Time Clock */
#define CNS3XXX_RTC_BASE_VIRT			0xFFF06000

#define RTC_SEC_OFFSET				0x00
#define RTC_MIN_OFFSET				0x04
#define RTC_HOUR_OFFSET				0x08
#define RTC_DAY_OFFSET				0x0C
#define RTC_SEC_ALM_OFFSET			0x10
#define RTC_MIN_ALM_OFFSET			0x14
#define RTC_HOUR_ALM_OFFSET			0x18
#define RTC_REC_OFFSET				0x1C
#define RTC_CTRL_OFFSET				0x20
#define RTC_INTR_STS_OFFSET			0x34

#define CNS3XXX_MISC_BASE			0x76000000	/* Misc Control */
#define CNS3XXX_MISC_BASE_VIRT			0xFB000000	/* Misc Control */

#define CNS3XXX_PM_BASE				0x77000000	/* Power Management Control */
#define CNS3XXX_PM_BASE_VIRT			0xFB001000

#define PM_CLK_GATE_OFFSET			0x00
#define PM_SOFT_RST_OFFSET			0x04
#define PM_HS_CFG_OFFSET			0x08
#define PM_CACTIVE_STA_OFFSET			0x0C
#define PM_PWR_STA_OFFSET			0x10
#define PM_SYS_CLK_CTRL_OFFSET			0x14
#define PM_PLL_LCD_I2S_CTRL_OFFSET		0x18
#define PM_PLL_HM_PD_OFFSET			0x1C

#define CNS3XXX_UART0_BASE			0x78000000	/* UART 0 */
#define CNS3XXX_UART0_BASE_VIRT			0xFB002000

#define CNS3XXX_UART1_BASE			0x78400000	/* UART 1 */
#define CNS3XXX_UART1_BASE_VIRT			0xFFF0A000

#define CNS3XXX_UART2_BASE			0x78800000	/* UART 2 */
#define CNS3XXX_UART2_BASE_VIRT			0xFFF0B000

#define CNS3XXX_DMAC_BASE			0x79000000	/* Generic DMA Control */
#define CNS3XXX_DMAC_BASE_VIRT			0xFFF0D000

#define CNS3XXX_CORESIGHT_BASE			0x7A000000	/* CoreSight */
#define CNS3XXX_CORESIGHT_BASE_VIRT		0xFFF0E000

#define CNS3XXX_CRYPTO_BASE			0x7B000000	/* Crypto */
#define CNS3XXX_CRYPTO_BASE_VIRT		0xFFF0F000

#define CNS3XXX_I2S_BASE			0x7C000000	/* I2S */
#define CNS3XXX_I2S_BASE_VIRT			0xFFF10000

#define CNS3XXX_TIMER1_2_3_BASE			0x7C800000	/* Timer */
#define CNS3XXX_TIMER1_2_3_BASE_VIRT		0xFB003000

#define TIMER1_COUNTER_OFFSET			0x00
#define TIMER1_AUTO_RELOAD_OFFSET		0x04
#define TIMER1_MATCH_V1_OFFSET			0x08
#define TIMER1_MATCH_V2_OFFSET			0x0C

#define TIMER2_COUNTER_OFFSET			0x10
#define TIMER2_AUTO_RELOAD_OFFSET		0x14
#define TIMER2_MATCH_V1_OFFSET			0x18
#define TIMER2_MATCH_V2_OFFSET			0x1C

#define TIMER1_2_CONTROL_OFFSET			0x30
#define TIMER1_2_INTERRUPT_STATUS_OFFSET	0x34
#define TIMER1_2_INTERRUPT_MASK_OFFSET		0x38

#define TIMER_FREERUN_OFFSET			0x40
#define TIMER_FREERUN_CONTROL_OFFSET		0x44

#define CNS3XXX_HCIE_BASE			0x7D000000	/* HCIE Control */
#define CNS3XXX_HCIE_BASE_VIRT			0xFFF30000

#define CNS3XXX_RAID_BASE			0x7E000000	/* RAID Control */
#define CNS3XXX_RAID_BASE_VIRT			0xFFF12000

#define CNS3XXX_AXI_IXC_BASE			0x7F000000	/* AXI IXC */
#define CNS3XXX_AXI_IXC_BASE_VIRT		0xFFF13000

#define CNS3XXX_CLCD_BASE			0x80000000	/* LCD Control */
#define CNS3XXX_CLCD_BASE_VIRT			0xFFF14000

#define CNS3XXX_USBOTG_BASE			0x81000000	/* USB OTG Control */
#define CNS3XXX_USBOTG_BASE_VIRT		0xFFF15000

#define CNS3XXX_USB_BASE			0x82000000	/* USB Host Control */

#define CNS3XXX_SATA2_BASE			0x83000000	/* SATA */
#define CNS3XXX_SATA2_SIZE			SZ_16M
#define CNS3XXX_SATA2_BASE_VIRT			0xFFF17000

#define CNS3XXX_CAMERA_BASE			0x84000000	/* Camera Interface */
#define CNS3XXX_CAMERA_BASE_VIRT		0xFFF18000

#define CNS3XXX_SDIO_BASE			0x85000000	/* SDIO */
#define CNS3XXX_SDIO_BASE_VIRT			0xFFF19000

#define CNS3XXX_I2S_TDM_BASE			0x86000000	/* I2S TDM */
#define CNS3XXX_I2S_TDM_BASE_VIRT		0xFFF1A000

#define CNS3XXX_2DG_BASE			0x87000000	/* 2D Graphic Control */
#define CNS3XXX_2DG_BASE_VIRT			0xFFF1B000

#define CNS3XXX_USB_OHCI_BASE			0x88000000	/* USB OHCI */

#define CNS3XXX_L2C_BASE			0x92000000	/* L2 Cache Control */
#define CNS3XXX_L2C_BASE_VIRT			0xFFF27000

#define CNS3XXX_PCIE0_MEM_BASE			0xA0000000	/* PCIe Port 0 IO/Memory Space */
#define CNS3XXX_PCIE0_MEM_BASE_VIRT		0xE0000000

#define CNS3XXX_PCIE0_HOST_BASE			0xAB000000	/* PCIe Port 0 RC Base */
#define CNS3XXX_PCIE0_HOST_BASE_VIRT		0xE1000000

#define CNS3XXX_PCIE0_IO_BASE			0xAC000000	/* PCIe Port 0 */
#define CNS3XXX_PCIE0_IO_BASE_VIRT		0xE2000000

#define CNS3XXX_PCIE0_CFG0_BASE			0xAD000000	/* PCIe Port 0 CFG Type 0 */
#define CNS3XXX_PCIE0_CFG0_BASE_VIRT		0xE3000000

#define CNS3XXX_PCIE0_CFG1_BASE			0xAE000000	/* PCIe Port 0 CFG Type 1 */
#define CNS3XXX_PCIE0_CFG1_BASE_VIRT		0xE4000000

#define CNS3XXX_PCIE0_MSG_BASE			0xAF000000	/* PCIe Port 0 Message Space */
#define CNS3XXX_PCIE0_MSG_BASE_VIRT		0xE5000000

#define CNS3XXX_PCIE1_MEM_BASE			0xB0000000	/* PCIe Port 1 IO/Memory Space */
#define CNS3XXX_PCIE1_MEM_BASE_VIRT		0xE8000000

#define CNS3XXX_PCIE1_HOST_BASE			0xBB000000	/* PCIe Port 1 RC Base */
#define CNS3XXX_PCIE1_HOST_BASE_VIRT		0xE9000000

#define CNS3XXX_PCIE1_IO_BASE			0xBC000000	/* PCIe Port 1 */
#define CNS3XXX_PCIE1_IO_BASE_VIRT		0xEA000000

#define CNS3XXX_PCIE1_CFG0_BASE			0xBD000000	/* PCIe Port 1 CFG Type 0 */
#define CNS3XXX_PCIE1_CFG0_BASE_VIRT		0xEB000000

#define CNS3XXX_PCIE1_CFG1_BASE			0xBE000000	/* PCIe Port 1 CFG Type 1 */
#define CNS3XXX_PCIE1_CFG1_BASE_VIRT		0xEC000000

#define CNS3XXX_PCIE1_MSG_BASE			0xBF000000	/* PCIe Port 1 Message Space */
#define CNS3XXX_PCIE1_MSG_BASE_VIRT		0xED000000

/*
 * Testchip peripheral and fpga gic regions
 */
#define CNS3XXX_TC11MP_SCU_BASE			0x90000000	/* IRQ, Test chip */
#define CNS3XXX_TC11MP_SCU_BASE_VIRT		0xFB004000

#define CNS3XXX_TC11MP_GIC_CPU_BASE		0x90000100	/* Test chip interrupt controller CPU interface */
#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT	(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)

#define CNS3XXX_TC11MP_TWD_BASE			0x90000600
#define CNS3XXX_TC11MP_TWD_BASE_VIRT		(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)

#define CNS3XXX_TC11MP_GIC_DIST_BASE		0x90001000	/* Test chip interrupt controller distributor */
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT	(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)

#define CNS3XXX_TC11MP_L220_BASE		0x92002000	/* L220 registers */
#define CNS3XXX_TC11MP_L220_BASE_VIRT		0xFF002000

/*
 * Misc block
 */
#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))

#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP(0x00)
#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP(0x04)
#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP(0x08)
#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP(0x0C)
#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP(0x10)
#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP(0x14)
#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP(0x18)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP(0x1C)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP(0x20)
#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x24)
#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x28)
#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x2C)
#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x30)
#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP(0x34)
#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP(0x40)
#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP(0x44)
#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP(0x48)
#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP(0x4C)
#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP(0x50)
#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP(0x54)

#define MISC_SATA_POWER_MODE			MISC_MEM_MAP(0x310)

#define MISC_USB_CFG_REG			MISC_MEM_MAP(0x800)
#define MISC_USB_STS_REG			MISC_MEM_MAP(0x804)
#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP(0x808)
#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP(0x80c)
#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP(0x810)
#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP(0x814)

#define MISC_PCIEPHY_CMCTL(x)			MISC_MEM_MAP(0x900 + (x) * 0x004)
#define MISC_PCIEPHY_CTL(x)			MISC_MEM_MAP(0x940 + (x) * 0x100)
#define MISC_PCIE_AXIS_AWMISC(x)		MISC_MEM_MAP(0x944 + (x) * 0x100)
#define MISC_PCIE_AXIS_ARMISC(x)		MISC_MEM_MAP(0x948 + (x) * 0x100)
#define MISC_PCIE_AXIS_RMISC(x)			MISC_MEM_MAP(0x94C + (x) * 0x100)
#define MISC_PCIE_AXIS_BMISC(x)			MISC_MEM_MAP(0x950 + (x) * 0x100)
#define MISC_PCIE_AXIM_RMISC(x)			MISC_MEM_MAP(0x954 + (x) * 0x100)
#define MISC_PCIE_AXIM_BMISC(x)			MISC_MEM_MAP(0x958 + (x) * 0x100)
#define MISC_PCIE_CTRL(x)			MISC_MEM_MAP(0x95C + (x) * 0x100)
#define MISC_PCIE_PM_DEBUG(x)			MISC_MEM_MAP(0x960 + (x) * 0x100)
#define MISC_PCIE_RFC_DEBUG(x)			MISC_MEM_MAP(0x964 + (x) * 0x100)
#define MISC_PCIE_CXPL_DEBUGL(x)		MISC_MEM_MAP(0x968 + (x) * 0x100)
#define MISC_PCIE_CXPL_DEBUGH(x)		MISC_MEM_MAP(0x96C + (x) * 0x100)
#define MISC_PCIE_DIAG_DEBUGH(x)		MISC_MEM_MAP(0x970 + (x) * 0x100)
#define MISC_PCIE_W1CLR(x)			MISC_MEM_MAP(0x974 + (x) * 0x100)
#define MISC_PCIE_INT_MASK(x)			MISC_MEM_MAP(0x978 + (x) * 0x100)
#define MISC_PCIE_INT_STATUS(x)			MISC_MEM_MAP(0x97C + (x) * 0x100)

/*
 * Power management and clock control
 */
#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))

#define PM_CLK_GATE_REG					PMU_MEM_MAP(0x000)
#define PM_SOFT_RST_REG					PMU_MEM_MAP(0x004)
#define PM_HS_CFG_REG					PMU_MEM_MAP(0x008)
#define PM_CACTIVE_STA_REG				PMU_MEM_MAP(0x00C)
#define PM_PWR_STA_REG					PMU_MEM_MAP(0x010)
#define PM_CLK_CTRL_REG					PMU_MEM_MAP(0x014)
#define PM_PLL_LCD_I2S_CTRL_REG				PMU_MEM_MAP(0x018)
#define PM_PLL_HM_PD_CTRL_REG				PMU_MEM_MAP(0x01C)
#define PM_REGULAT_CTRL_REG				PMU_MEM_MAP(0x020)
#define PM_WDT_CTRL_REG					PMU_MEM_MAP(0x024)
#define PM_WU_CTRL0_REG					PMU_MEM_MAP(0x028)
#define PM_WU_CTRL1_REG					PMU_MEM_MAP(0x02C)
#define PM_CSR_REG					PMU_MEM_MAP(0x030)

/* PM_CLK_GATE_REG */
#define PM_CLK_GATE_REG_OFFSET_SDIO			(25)
#define PM_CLK_GATE_REG_OFFSET_GPU			(24)
#define PM_CLK_GATE_REG_OFFSET_CIM			(23)
#define PM_CLK_GATE_REG_OFFSET_LCDC			(22)
#define PM_CLK_GATE_REG_OFFSET_I2S			(21)
#define PM_CLK_GATE_REG_OFFSET_RAID			(20)
#define PM_CLK_GATE_REG_OFFSET_SATA			(19)
#define PM_CLK_GATE_REG_OFFSET_PCIE(x)			(17 + (x))
#define PM_CLK_GATE_REG_OFFSET_USB_HOST			(16)
#define PM_CLK_GATE_REG_OFFSET_USB_OTG			(15)
#define PM_CLK_GATE_REG_OFFSET_TIMER			(14)
#define PM_CLK_GATE_REG_OFFSET_CRYPTO			(13)
#define PM_CLK_GATE_REG_OFFSET_HCIE			(12)
#define PM_CLK_GATE_REG_OFFSET_SWITCH			(11)
#define PM_CLK_GATE_REG_OFFSET_GPIO			(10)
#define PM_CLK_GATE_REG_OFFSET_UART3			(9)
#define PM_CLK_GATE_REG_OFFSET_UART2			(8)
#define PM_CLK_GATE_REG_OFFSET_UART1			(7)
