/*
 *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
 *
 *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
 *                     Sony Software Development Center Europe (SDCE), Brussels
 *
 *  This file is based on the following documentation:
 *
 *	NEC Vrc 5074 System Controller Data Sheet, June 1998
 */

#ifndef _ASM_NILE4_H
#define _ASM_NILE4_H

#define NILE4_BASE		0xbfa00000
#define NILE4_SIZE		0x00200000		/* 2 MB */


    /*
     *  Physical Device Address Registers (PDARs)
     */

#define NILE4_SDRAM0	0x0000	/* SDRAM Bank 0 [R/W] */
#define NILE4_SDRAM1	0x0008	/* SDRAM Bank 1 [R/W] */
#define NILE4_DCS2	0x0010	/* Device Chip-Select 2 [R/W] */
#define NILE4_DCS3	0x0018	/* Device Chip-Select 3 [R/W] */
#define NILE4_DCS4	0x0020	/* Device Chip-Select 4 [R/W] */
#define NILE4_DCS5	0x0028	/* Device Chip-Select 5 [R/W] */
#define NILE4_DCS6	0x0030	/* Device Chip-Select 6 [R/W] */
#define NILE4_DCS7	0x0038	/* Device Chip-Select 7 [R/W] */
#define NILE4_DCS8	0x0040	/* Device Chip-Select 8 [R/W] */
#define NILE4_PCIW0	0x0060	/* PCI Address Window 0 [R/W] */
#define NILE4_PCIW1	0x0068	/* PCI Address Window 1 [R/W] */
#define NILE4_INTCS	0x0070	/* Controller Internal Registers and Devices */
				/* [R/W] */
#define NILE4_BOOTCS	0x0078	/* Boot ROM Chip-Select [R/W] */


    /*
     *  CPU Interface Registers
     */

#define NILE4_CPUSTAT	0x0080	/* CPU Status [R/W] */
#define NILE4_INTCTRL	0x0088	/* Interrupt Control [R/W] */
#define NILE4_INTSTAT0	0x0090	/* Interrupt Status 0 [R] */
#define NILE4_INTSTAT1	0x0098	/* Interrupt Status 1 and CPU Interrupt */
				/* Enable [R/W] */
#define NILE4_INTCLR	0x00A0	/* Interrupt Clear [R/W] */
#define NILE4_INTPPES	0x00A8	/* PCI Interrupt Control [R/W] */


    /*
     *  Memory-Interface Registers
     */

#define NILE4_MEMCTRL	0x00C0	/* Memory Control */
#define NILE4_ACSTIME	0x00C8	/* Memory Access Timing [R/W] */
#define NILE4_CHKERR	0x00D0	/* Memory Check Error Status [R] */


    /*
     *  PCI-Bus Registers
     */

#define NILE4_PCICTRL	0x00E0	/* PCI Control [R/W] */
#define NILE4_PCIARB	0x00E8	/* PCI Arbiter [R/W] */
#define NILE4_PCIINIT0	0x00F0	/* PCI Master (Initiator) 0 [R/W] */
#define NILE4_PCIINIT1	0x00F8	/* PCI Master (Initiator) 1 [R/W] */
#define NILE4_PCIERR	0x00B8	/* PCI Error [R/W] */


    /*
     *  Local-Bus Registers
     */

#define NILE4_LCNFG	0x0100	/* Local Bus Configuration [R/W] */
#define NILE4_LCST2	0x0110	/* Local Bus Chip-Select Timing 2 [R/W] */
#define NILE4_LCST3	0x0118	/* Local Bus Chip-Select Timing 3 [R/W] */
#define NILE4_LCST4	0x0120	/* Local Bus Chip-Select Timing 4 [R/W] */
#define NILE4_LCST5	0x0128	/* Local Bus Chip-Select Timing 5 [R/W] */
#define NILE4_LCST6	0x0130	/* Local Bus Chip-Select Timing 6 [R/W] */
#define NILE4_LCST7	0x0138	/* Local Bus Chip-Select Timing 7 [R/W] */
#define NILE4_LCST8	0x0140	/* Local Bus Chip-Select Timing 8 [R/W] */
#define NILE4_DCSFN	0x0150	/* Device Chip-Select Muxing and Output */
				/* Enables [R/W] */
#define NILE4_DCSIO	0x0158	/* Device Chip-Selects As I/O Bits [R/W] */
#define NILE4_BCST	0x0178	/* Local Boot Chip-Select Timing [R/W] */


    /*
     *  DMA Registers
     */

#define NILE4_DMACTRL0	0x0180	/* DMA Control 0 [R/W] */
#define NILE4_DMASRCA0	0x0188	/* DMA Source Address 0 [R/W] */
#define NILE4_DMADESA0	0x0190	/* DMA Destination Address 0 [R/W] */
#define NILE4_DMACTRL1	0x0198	/* DMA Control 1 [R/W] */
#define NILE4_DMASRCA1	0x01A0	/* DMA Source Address 1 [R/W] */
#define NILE4_DMADESA1	0x01A8	/* DMA Destination Address 1 [R/W] */


    /*
     *  Timer Registers
     */

#define NILE4_T0CTRL	0x01C0	/* SDRAM Refresh Control [R/W] */
#define NILE4_T0CNTR	0x01C8	/* SDRAM Refresh Counter [R/W] */
#define NILE4_T1CTRL	0x01D0	/* CPU-Bus Read Time-Out Control [R/W] */
#define NILE4_T1CNTR	0x01D8	/* CPU-Bus Read Time-Out Counter [R/W] */
#define NILE4_T2CTRL	0x01E0	/* General-Purpose Timer Control [R/W] */
#define NILE4_T2CNTR	0x01E8	/* General-Purpose Timer Counter [R/W] */
#define NILE4_T3CTRL	0x01F0	/* Watchdog Timer Control [R/W] */
#define NILE4_T3CNTR	0x01F8	/* Watchdog Timer Counter [R/W] */


    /*
     *  PCI Configuration Space Registers
     */

#define NILE4_PCI_BASE	0x0200

#define NILE4_VID	0x0200	/* PCI Vendor ID [R] */
