/*
 * OMAP4 Clock domains framework
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"

#include "cm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm44xx.h"
#include "prcm_mpu44xx.h"

/* Static Dependencies for OMAP4 Clock Domains */

static struct clkdm_dep d2d_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ NULL },
};

static struct clkdm_dep ducati_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_gfx_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ .clkdm_name = "tesla_clkdm" },
	{ NULL },
};

static struct clkdm_dep iss_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ducati_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ NULL },
};

static struct clkdm_dep mpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ducati_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_dss_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_gfx_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_secure_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ .clkdm_name = "tesla_clkdm" },
	{ NULL },
};

static struct clkdm_dep tesla_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "ivahd_clkdm" },
	{ .clkdm_name = "l3_1_clkdm" },
	{ .clkdm_name = "l3_2_clkdm" },
	{ .clkdm_name = "l3_emif_clkdm" },
	{ .clkdm_name = "l3_init_clkdm" },
	{ .clkdm_name = "l4_cfg_clkdm" },
	{ .clkdm_name = "l4_per_clkdm" },
	{ .clkdm_name = "l4_wkup_clkdm" },
	{ NULL },
};

static struct clockdomain l4_cefuse_44xx_clkdm = {
	.name		  = "l4_cefuse_clkdm",
	.pwrdm		  = { .name = "cefuse_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CEFUSE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l4_cfg_44xx_clkdm = {
	.name		  = "l4_cfg_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_CORE_INST,
	.clkdm_offs	  = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
	.dep_bit	  = OMAP4430_L4CFG_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain tesla_44xx_clkdm = {
	.name		  = "tesla_clkdm",
	.pwrdm		  = { .name = "tesla_pwrdm" },
	.prcm_partition	  = OMAP4430_CM1_PARTITION,
	.cm_inst	  = OMAP4430_CM1_TESLA_INST,
	.clkdm_offs	  = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
	.dep_bit	  = OMAP4430_TESLA_STATDEP_SHIFT,
	.wkdep_srcs	  = tesla_wkup_sleep_deps,
	.sleepdep_srcs	  = tesla_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l3_gfx_44xx_clkdm = {
	.name		  = "l3_gfx_clkdm",
	.pwrdm		  = { .name = "gfx_pwrdm" },
	.prcm_partition	  = OMAP4430_CM2_PARTITION,
	.cm_inst	  = OMAP4430_CM2_GFX_INST,
	.clkdm_offs	  = OMAP4430_CM2_GFX_GFX_CDOFFS,
	.dep_bit	  = OMAP4430_GFX_STATDEP_SHIFT,
	.wkdep_srcs	  = l3_gfx_wkup_sleep_deps,
	.sleepdep_srcs	  = l3_gfx_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

