/*
 * Copyright 2005-2010 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H

/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)

/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
#define bfin_read_SWRST()                    bfin_read16(SWRST)
#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)

/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)

/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)

/* DMA Traffic controls */
#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)
#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)
#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)

/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
#define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
#define bfin_read_FIO_MASKA_C()              bfin_read16(FIO_MASKA_C)
#define bfin_write_FIO_MASKA_C(val)          bfin_write16(FIO_MASKA_C,val)
#define bfin_read_FIO_MASKA_S()              bfin_read16(FIO_MASKA_S)
#define bfin_write_FIO_MASKA_S(val)          bfin_write16(FIO_MASKA_S,val)
#define bfin_read_FIO_MASKB_C()              bfin_read16(FIO_MASKB_C)
#define bfin_write_FIO_MASKB_C(val)          bfin_write16(FIO_MASKB_C,val)
#define bfin_read_FIO_MASKB_S()              bfin_read16(FIO_MASKB_S)
#define bfin_write_FIO_MASKB_S(val)          bfin_write16(FIO_MASKB_S,val)
#define bfin_read_FIO_POLAR()                bfin_read16(FIO_POLAR)
#define bfin_write_FIO_POLAR(val)            bfin_write16(FIO_POLAR,val)
#define bfin_read_FIO_EDGE()                 bfin_read16(FIO_EDGE)
#define bfin_write_FIO_EDGE(val)             bfin_write16(FIO_EDGE,val)
#define bfin_read_FIO_BOTH()                 bfin_read16(FIO_BOTH)
#define bfin_write_FIO_BOTH(val)             bfin_write16(FIO_BOTH,val)
#define bfin_read_FIO_INEN()                 bfin_read16(FIO_INEN)
#define bfin_write_FIO_INEN(val)             bfin_write16(FIO_INEN,val)
#define bfin_read_FIO_MASKA_D()              bfin_read16(FIO_MASKA_D)
#define bfin_write_FIO_MASKA_D(val)          bfin_write16(FIO_MASKA_D,val)
#define bfin_read_FIO_MASKA_T()              bfin_read16(FIO_MASKA_T)
#define bfin_write_FIO_MASKA_T(val)          bfin_write16(FIO_MASKA_T,val)
#define bfin_read_FIO_MASKB_D()              bfin_read16(FIO_MASKB_D)
#define bfin_write_FIO_MASKB_D(val)          bfin_write16(FIO_MASKB_D,val)
#define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
#define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)

#if ANOMALY_05000311
/* Keep at the CPP expansion to avoid circular header dependency loops */
#define BFIN_WRITE_FIO_FLAG(name, val) \
	do { \
		unsigned long __flags; \
		__flags = hard_local_irq_save(); \
		bfin_write16(FIO_FLAG_##name, val); \
		bfin_read_CHIPID(); \
		hard_local_irq_restore(__flags); \
	} while (0)
#define bfin_write_FIO_FLAG_D(val)           BFIN_WRITE_FIO_FLAG(D, val)
#define bfin_write_FIO_FLAG_C(val)           BFIN_WRITE_FIO_FLAG(C, val)
#define bfin_write_FIO_FLAG_S(val)           BFIN_WRITE_FIO_FLAG(S, val)
#define bfin_write_FIO_FLAG_T(val)           BFIN_WRITE_FIO_FLAG(T, val)

#define BFIN_READ_FIO_FLAG(name) \
	({ \
		unsigned long __flags; \
		u16 __ret; \
		__flags = hard_local_irq_save(); \
		__ret = bfin_read16(FIO_FLAG_##name); \
		bfin_read_CHIPID(); \
		hard_local_irq_restore(__flags); \
		__ret; \
	})
#define bfin_read_FIO_FLAG_D()               BFIN_READ_FIO_FLAG(D)
#define bfin_read_FIO_FLAG_C()               BFIN_READ_FIO_FLAG(C)
#define bfin_read_FIO_FLAG_S()               BFIN_READ_FIO_FLAG(S)
#define bfin_read_FIO_FLAG_T()               BFIN_READ_FIO_FLAG(T)

#else
#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
#endif

/* DMA Controller */
#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)

#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)

#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)

#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
