/*
 * Copyright (C) 2009 Nokia
 * Copyright (C) 2009 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define OMAP3_CONTROL_PADCONF_MUX_PBASE				0x48002030LU

#define OMAP3_MUX(mode0, mux_value)					\
{									\
	.reg_offset	= (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET),	\
	.value		= (mux_value),					\
}

/*
 * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
 *
 * Extracted from the TRM.  Add 0x48002030 to these values to get the
 * absolute addresses.  The name in the macro is the mode-0 name of
 * the pin.  NOTE: These registers are 16-bits wide.
 *
 * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
 * of CHASSIS for some registers. For the defines, we follow the
 * 36XX naming, and use SDMMC and CHASSIS.
 */
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET			0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET			0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET			0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET			0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET			0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET			0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET			0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET			0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET			0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET			0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET			0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET			0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET			0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET			0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET			0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET			0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET			0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET			0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET			0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET			0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET			0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET			0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET			0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET			0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET			0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET			0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET			0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET			0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET			0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET			0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET			0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET			0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET			0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET			0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET			0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET			0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET			0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET			0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET			0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET			0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET			0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET			0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET			0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET			0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET			0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET			0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET			0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET			0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET			0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET			0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET			0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET			0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET			0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET			0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET			0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET			0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET			0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET			0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET			0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET			0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET			0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET			0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET			0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET			0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET			0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET			0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET			0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET			0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET			0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET			0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET			0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET			0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET		0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET			0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET			0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET		0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET			0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET			0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET			0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET			0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET			0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET			0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET			0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET			0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET			0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET			0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET			0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET			0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET			0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET			0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET			0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET			0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET			0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET			0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET			0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET			0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET			0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET			0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET			0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET			0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET			0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET			0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET			0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET			0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET			0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET			0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET			0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET			0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET			0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET			0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET			0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET			0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET			0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET			0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET			0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET			0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET			0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET			0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET			0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET			0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET			0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET			0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET			0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET			0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET			0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET			0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET			0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET			0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET			0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET			0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET			0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET			0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET			0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET			0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET			0x10c
