//----------------------------------------------------------------------------
//
//  File generated by S1D13806CFG.EXE
//
//  Copyright (c) 2000,2001 Epson Research and Development, Inc.
//  All rights reserved.
//
//----------------------------------------------------------------------------

// Panel:  (active)  640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)

#define SWIVEL_VIEW		0	/* 0:none, 1:90 not completed */

static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {

    {0x0001,0x00},   // Miscellaneous Register
    {0x01FC,0x00},   // Display Mode Register
#if defined(CONFIG_PLAT_MAPPI)
    {0x0004,0x00},   // General IO Pins Configuration Register 0
    {0x0005,0x00},   // General IO Pins Configuration Register 1
    {0x0008,0x00},   // General IO Pins Control Register 0
    {0x0009,0x00},   // General IO Pins Control Register 1
    {0x0010,0x00},   // Memory Clock Configuration Register
    {0x0014,0x00},   // LCD Pixel Clock Configuration Register
    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
    {0x001C,0x00},   // MediaPlug Clock Configuration Register
/*
 * .. 10MHz: 0x00
 * .. 30MHz: 0x01
 * 30MHz ..: 0x02
 */
    {0x001E,0x02},   // CPU To Memory Wait State Select Register
    {0x0021,0x02},   // DRAM Refresh Rate Register
    {0x002A,0x11},   // DRAM Timings Control Register 0
    {0x002B,0x13},   // DRAM Timings Control Register 1
    {0x0020,0x80},   // Memory Configuration Register
    {0x0030,0x25},   // Panel Type Register
    {0x0031,0x00},   // MOD Rate Register
    {0x0032,0x4F},   // LCD Horizontal Display Width Register
    {0x0034,0x12},   // LCD Horizontal Non-Display Period Register
    {0x0035,0x01},   // TFT FPLINE Start Position Register
    {0x0036,0x0B},   // TFT FPLINE Pulse Width Register
    {0x0038,0xDF},   // LCD Vertical Display Height Register 0
    {0x0039,0x01},   // LCD Vertical Display Height Register 1
    {0x003A,0x2C},   // LCD Vertical Non-Display Period Register
    {0x003B,0x0A},   // TFT FPFRAME Start Position Register
    {0x003C,0x01},   // TFT FPFRAME Pulse Width Register

    {0x0041,0x00},   // LCD Miscellaneous Register
    {0x0042,0x00},   // LCD Display Start Address Register 0
    {0x0043,0x00},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2

#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
    {0x0004,0x07},   // GPIO[0:7] direction
    {0x0005,0x00},   // GPIO[8:12] direction
    {0x0008,0x00},   // GPIO[0:7] data
    {0x0009,0x00},   // GPIO[8:12] data
    {0x0008,0x04},   // LCD panel Vcc on
    {0x0008,0x05},   // LCD panel reset
    {0x0010,0x01},   // Memory Clock Configuration Register
    {0x0014,0x30},   // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
    {0x001C,0x00},   // MediaPlug Clock Configuration Register(10MHz)
    {0x001E,0x00},   // CPU To Memory Wait State Select Register
    {0x0020,0x80},   // Memory Configuration Register
    {0x0021,0x03},   // DRAM Refresh Rate Register
    {0x002A,0x00},   // DRAM Timings Control Register 0
    {0x002B,0x01},   // DRAM Timings Control Register 1
    {0x0030,0x25},   // Panel Type Register
    {0x0031,0x00},   // MOD Rate Register
    {0x0032,0x1d},   // LCD Horizontal Display Width Register
    {0x0034,0x05},   // LCD Horizontal Non-Display Period Register
    {0x0035,0x01},   // TFT FPLINE Start Position Register
    {0x0036,0x01},   // TFT FPLINE Pulse Width Register
    {0x0038,0x3F},   // LCD Vertical Display Height Register 0
    {0x0039,0x01},   // LCD Vertical Display Height Register 1
    {0x003A,0x0b},   // LCD Vertical Non-Display Period Register
    {0x003B,0x07},   // TFT FPFRAME Start Position Register
    {0x003C,0x02},   // TFT FPFRAME Pulse Width Register

    {0x0041,0x00},   // LCD Miscellaneous Register
#if (SWIVEL_VIEW == 0)
    {0x0042,0x00},   // LCD Display Start Address Register 0
    {0x0043,0x00},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2

#elif (SWIVEL_VIEW == 1)
    // 1024 - W(320) = 0x2C0
    {0x0042,0xC0},   // LCD Display Start Address Register 0
    {0x0043,0x02},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 2
