/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __ASM_ARCH_MSM_IRQS_8960_H
#define __ASM_ARCH_MSM_IRQS_8960_H

/* MSM ACPU Interrupt Numbers */

/* 0-15:  STI/SGI (software triggered/generated interrupts)
   16-31: PPI (private peripheral interrupts)
   32+:   SPI (shared peripheral interrupts) */

#define GIC_PPI_START 16
#define GIC_SPI_START 32

#define INT_VGIC				(GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP			(GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP			(GIC_PPI_START + 2)
#define INT_GP_TIMER2_EXP			(GIC_PPI_START + 3)
#define WDT0_ACCSCSSNBARK_INT			(GIC_PPI_START + 4)
#define WDT1_ACCSCSSNBARK_INT			(GIC_PPI_START + 5)
#define AVS_SVICINT				(GIC_PPI_START + 6)
#define AVS_SVICINTSWDONE			(GIC_PPI_START + 7)
#define CPU_DBGCPUXCOMMRXFULL			(GIC_PPI_START + 8)
#define CPU_DBGCPUXCOMMTXEMPTY			(GIC_PPI_START + 9)
#define CPU_SICCPUXPERFMONIRPTREQ		(GIC_PPI_START + 10)
#define SC_AVSCPUXDOWN				(GIC_PPI_START + 11)
#define SC_AVSCPUXUP				(GIC_PPI_START + 12)
#define SC_SICCPUXACGIRPTREQ			(GIC_PPI_START + 13)
#define SC_SICCPUXEXTFAULTIRPTREQ		(GIC_PPI_START + 14)
/* PPI 15 is unused */

#define SC_SICMPUIRPTREQ			(GIC_SPI_START + 0)
#define SC_SICL2IRPTREQ				(GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ			(GIC_SPI_START + 2)
#define SC_SICAGCIRPTREQ			(GIC_SPI_START + 3)
#define TLMM_APCC_DIR_CONN_IRQ_0		(GIC_SPI_START + 4)
#define TLMM_APCC_DIR_CONN_IRQ_1		(GIC_SPI_START + 5)
#define TLMM_APCC_DIR_CONN_IRQ_2		(GIC_SPI_START + 6)
#define TLMM_APCC_DIR_CONN_IRQ_3		(GIC_SPI_START + 7)
#define TLMM_APCC_DIR_CONN_IRQ_4		(GIC_SPI_START + 8)
#define TLMM_APCC_DIR_CONN_IRQ_5		(GIC_SPI_START + 9)
#define TLMM_APCC_DIR_CONN_IRQ_6		(GIC_SPI_START + 10)
#define TLMM_APCC_DIR_CONN_IRQ_7		(GIC_SPI_START + 11)
#define TLMM_APCC_DIR_CONN_IRQ_8		(GIC_SPI_START + 12)
#define TLMM_APCC_DIR_CONN_IRQ_9		(GIC_SPI_START + 13)
#define PM8921_SEC_IRQ_103			(GIC_SPI_START + 14)
#define PM8018_SEC_IRQ_106			(GIC_SPI_START + 15)
#define TLMM_APCC_SUMMARY_IRQ			(GIC_SPI_START + 16)
#define SPDM_RT_1_IRQ				(GIC_SPI_START + 17)
#define SPDM_DIAG_IRQ				(GIC_SPI_START + 18)
#define RPM_APCC_CPU0_GP_HIGH_IRQ		(GIC_SPI_START + 19)
#define RPM_APCC_CPU0_GP_MEDIUM_IRQ		(GIC_SPI_START + 20)
#define RPM_APCC_CPU0_GP_LOW_IRQ		(GIC_SPI_START + 21)
#define RPM_APCC_CPU0_WAKE_UP_IRQ		(GIC_SPI_START + 22)
#define RPM_APCC_CPU1_GP_HIGH_IRQ		(GIC_SPI_START + 23)
#define RPM_APCC_CPU1_GP_MEDIUM_IRQ		(GIC_SPI_START + 24)
#define RPM_APCC_CPU1_GP_LOW_IRQ		(GIC_SPI_START + 25)
#define RPM_APCC_CPU1_WAKE_UP_IRQ		(GIC_SPI_START + 26)
#define SSBI2_2_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 27)
#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 28)
#define SSBI2_1_SC_CPU0_SECURE_IRQ		(GIC_SPI_START + 29)
#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ		(GIC_SPI_START + 30)
#define MSMC_SC_SEC_CE_IRQ			(GIC_SPI_START + 31)
#define MSMC_SC_PRI_CE_IRQ			(GIC_SPI_START + 32)
#define SLIMBUS0_CORE_EE1_IRQ			(GIC_SPI_START + 33)
#define SLIMBUS0_BAM_EE1_IRQ			(GIC_SPI_START + 34)
#define Q6FW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 35)
#define Q6SW_WDOG_EXPIRED_IRQ			(GIC_SPI_START + 36)
#define MSS_TO_APPS_IRQ_0			(GIC_SPI_START + 37)
#define MSS_TO_APPS_IRQ_1			(GIC_SPI_START + 38)
#define MSS_TO_APPS_IRQ_2			(GIC_SPI_START + 39)
#define MSS_TO_APPS_IRQ_3			(GIC_SPI_START + 40)
#define MSS_TO_APPS_IRQ_4			(GIC_SPI_START + 41)
#define MSS_TO_APPS_IRQ_5			(GIC_SPI_START + 42)
#define MSS_TO_APPS_IRQ_6			(GIC_SPI_START + 43)
#define MSS_TO_APPS_IRQ_7			(GIC_SPI_START + 44)
#define MSS_TO_APPS_IRQ_8			(GIC_SPI_START + 45)
#define MSS_TO_APPS_IRQ_9			(GIC_SPI_START + 46)
#define VPE_IRQ					(GIC_SPI_START + 47)
#define VFE_IRQ					(GIC_SPI_START + 48)
#define VCODEC_IRQ				(GIC_SPI_START + 49)
#define TV_ENC_IRQ				(GIC_SPI_START + 50)
#define SMMU_VPE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 51)
#define SMMU_VPE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 52)
#define SMMU_VFE_CB_SC_SECURE_IRQ		(GIC_SPI_START + 53)
#define SMMU_VFE_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 54)
#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ		(GIC_SPI_START + 55)
#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 56)
#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ		(GIC_SPI_START + 57)
#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 58)
#define SMMU_ROT_CB_SC_SECURE_IRQ		(GIC_SPI_START + 59)
#define SMMU_ROT_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 60)
#define SMMU_MDP1_CB_SC_SECURE_IRQ		(GIC_SPI_START + 61)
#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 62)
#define SMMU_MDP0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 63)
#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 64)
#define SMMU_JPEGD_CB_SC_SECURE_IRQ		(GIC_SPI_START + 65)
#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 66)
#define SMMU_IJPEG_CB_SC_SECURE_IRQ		(GIC_SPI_START + 67)
#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 68)
#define SMMU_GFX3D_CB_SC_SECURE_IRQ		(GIC_SPI_START + 69)
#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ		(GIC_SPI_START + 70)
#define SMMU_GFX2D0_CB_SC_SECURE_IRQ		(GIC_SPI_START + 71)
#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ	(GIC_SPI_START + 72)
#define ROT_IRQ					(GIC_SPI_START + 73)
#define MMSS_FABRIC_IRQ				(GIC_SPI_START + 74)
#define MDP_IRQ					(GIC_SPI_START + 75)
#define JPEGD_IRQ				(GIC_SPI_START + 76)
#define JPEG_IRQ				(GIC_SPI_START + 77)
#define MMSS_IMEM_IRQ				(GIC_SPI_START + 78)
#define HDMI_IRQ				(GIC_SPI_START + 79)
#define GFX3D_IRQ				(GIC_SPI_START + 80)
#define GFX2D0_IRQ				(GIC_SPI_START + 81)
#define DSI1_IRQ				(GIC_SPI_START + 82)
#define CSI_1_IRQ				(GIC_SPI_START + 83)
#define CSI_0_IRQ				(GIC_SPI_START + 84)
#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ		(GIC_SPI_START + 85)
#define LPASS_SCSS_MIDI_IRQ			(GIC_SPI_START + 86)
#define LPASS_Q6SS_WDOG_EXPIRED			(GIC_SPI_START + 87)
#define LPASS_SCSS_GP_LOW_IRQ			(GIC_SPI_START + 88)
#define LPASS_SCSS_GP_MEDIUM_IRQ		(GIC_SPI_START + 89)
#define LPASS_SCSS_GP_HIGH_IRQ			(GIC_SPI_START + 90)
#define TOP_IMEM_IRQ				(GIC_SPI_START + 91)
#define FABRIC_SYS_IRQ				(GIC_SPI_START + 92)
#define FABRIC_APPS_IRQ				(GIC_SPI_START + 93)
#define USB1_HS_BAM_IRQ				(GIC_SPI_START + 94)
#define SDC4_BAM_IRQ				(GIC_SPI_START + 95)
#define SDC3_BAM_IRQ				(GIC_SPI_START + 96)
